soc/amd/stoneyridge/psp: fix check of MSR_PSP_ADDR contents

TEST=Checked documentation, but not verified on hardware.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06399ac9cb9c90701dbcba71cbc808a0d7e6ea0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index a7fead7..69db08d 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -45,7 +45,7 @@
 	 * the MSR instead. */
 	if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
 		psp_mmio = rdmsr(MSR_PSP_ADDR).lo;
-		if (psp_mmio == 0xffffffff) {
+		if (!psp_mmio) {
 			printk(BIOS_WARNING, "PSP: BAR hidden, MSR_PSP_ADDR uninitialized\n");
 			return 0;
 		}