tree 6a3250ac0a7c11e5f305e44e3e3629fbde79ebeb
parent 0d2c0019e284aea3b1889579782495afb6e52daf
author Martin Roth <martinroth@chromium.org> 1616532838 -0600
committer Felix Held <felix-coreboot@felixheld.de> 1618358451 +0000

soc/amd/cezanne: save chipset state to CBMEM

Guybrush complains that this is missing during the boot, so add it to
cezanne. I verified that the registers in gpio.c are correct.

BUG=b:184549804
TEST=Build and boot

Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>