soc/amd/cezanne: save chipset state to CBMEM
Guybrush complains that this is missing during the boot, so add it to
cezanne. I verified that the registers in gpio.c are correct.
BUG=b:184549804
TEST=Build and boot
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de3764c99fe89b962db88065575463b365ddaf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index a27b26d..7a1146f 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -50,6 +50,7 @@
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PM
+ select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
select SOC_AMD_COMMON_BLOCK_SMBUS
select SOC_AMD_COMMON_BLOCK_SMI
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 57c1961..573b353 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -4,6 +4,7 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h>
+#include <amdblocks/pmlib.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/api.h>
@@ -20,6 +21,9 @@
post_code(0x41);
+ /* Snapshot chipset state prior to any FSP call */
+ fill_chipset_state();
+
fsp_memory_init(acpi_is_wakeup_s3());
soc_update_apob_cache();