mb/google/cyan,intel/strago: Remove EC_GOOGLE_CHROMEEC tests
Boards have unconditional select EC_GOOGLE_CHROMEEC.
Change-Id: Id444c83fc40f908d2257e8ec2606f149722a9bde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c
index f69d4c4..912ae56 100644
--- a/src/mainboard/google/cyan/ec.c
+++ b/src/mainboard/google/cyan/ec.c
@@ -19,8 +19,7 @@
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
- if (CONFIG(EC_GOOGLE_CHROMEEC))
- google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
post_code(0xf1);
}
diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c
index 160b14b..693a72d 100644
--- a/src/mainboard/google/cyan/smihandler.c
+++ b/src/mainboard/google/cyan/smihandler.c
@@ -41,7 +41,6 @@
return 1;
}
-#if CONFIG(EC_GOOGLE_CHROMEEC)
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
@@ -65,7 +64,6 @@
return cmd;
}
-#endif
/*
* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
@@ -73,13 +71,11 @@
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
-#if CONFIG(EC_GOOGLE_CHROMEEC)
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
;
}
-#endif
}
void mainboard_smi_sleep(uint8_t slp_typ)
@@ -90,7 +86,6 @@
/* Disable USB charging if required */
switch (slp_typ) {
case ACPI_S3:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -100,12 +95,10 @@
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
-#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case ACPI_S5:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -115,7 +108,6 @@
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
-#endif
/* Disabling wake from SUS_GPIO1 (TOUCH INT) and
* SUS_GPIO7 (TRACKPAD INT) in North bank as they are not
@@ -129,7 +121,6 @@
break;
}
-#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
@@ -142,29 +133,24 @@
if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) {
lpc_set_low_power();
}
-#endif
}
int mainboard_smi_apmc(uint8_t apmc)
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
-#endif
break;
case APM_CNT_ACPI_DISABLE:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
-#endif
break;
}
return 0;
diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c
index f69d4c4..912ae56 100644
--- a/src/mainboard/intel/strago/ec.c
+++ b/src/mainboard/intel/strago/ec.c
@@ -19,8 +19,7 @@
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
- if (CONFIG(EC_GOOGLE_CHROMEEC))
- google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
post_code(0xf1);
}
diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c
index e770057..4116ed4 100644
--- a/src/mainboard/intel/strago/smihandler.c
+++ b/src/mainboard/intel/strago/smihandler.c
@@ -40,7 +40,6 @@
return 1;
}
-#if CONFIG(EC_GOOGLE_CHROMEEC)
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
@@ -64,7 +63,6 @@
return cmd;
}
-#endif
/*
* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
@@ -72,13 +70,11 @@
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
-#if CONFIG(EC_GOOGLE_CHROMEEC)
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
;
}
-#endif
}
void mainboard_smi_sleep(uint8_t slp_typ)
@@ -86,7 +82,6 @@
/* Disable USB charging if required */
switch (slp_typ) {
case ACPI_S3:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -96,12 +91,10 @@
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
-#endif
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
case ACPI_S5:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -111,11 +104,9 @@
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
-#endif
break;
}
-#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
@@ -127,29 +118,24 @@
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
lpc_set_low_power();
-#endif
}
int mainboard_smi_apmc(uint8_t apmc)
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
-#endif
break;
case APM_CNT_ACPI_DISABLE:
-#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
-#endif
break;
}
return 0;