tree 385d888ca0861b734b60168df563601032d8e8db
parent 8bde652241ecb8356540b3a418012d3c7e570ac3
author Mark Hasemeyer <markhas@google.com> 1695659807 -0600
committer Matt DeVillier <matt.devillier@amd.corp-partner.google.com> 1698932037 +0000

mb/google/guybrush: Set PS2K_IRQ to level/low

On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.

From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.

Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.

As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.

EC related CL here: https://crrev.com/c/4891663

BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
     -Flash new RW fw and verify keyboard is functional
     -`suspend_stress_test -c 1` and verify i8042 irq is removed as a
     wake source
     -`echo mem > /sys/power/state`. Press key and verify system wake
     from i8042.

Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>