mb/google/guybrush: Set PS2K_IRQ to level/low
On guybrush, keyboard presses are signaled by the EC via eSPI virtual
wire. The interrupt is shared with others and should be active low.
From 74bce48f1d4 ("mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarity"):
> The default state for the IRQ lines when the eSPI controller comes
> out of reset is high. This is because the IRQ lines are shared with
> the other IRQ sources using AND gates. This means that in order to
> not cause any spurious interrupts or miss any interrupts, the
> IO-APIC must use a low polarity trigger.
Setting `vw_irq_polarity` in the device tree provides an option to
invert interrupts from the eSPI controller, but the register is
initialized from verstage which is baked into RO.
As a workaround, the necessary interrupts on the EC have been
reconfigured to be active low, and we can modify the IO-APIC
accordingly.
EC related CL here: https://crrev.com/c/4891663
BUG=b:218874489
TEST=-`emerge-guybrush chromeos-ec coreboot chromeos-bootimage`
-Flash new RW fw and verify keyboard is functional
-`suspend_stress_test -c 1` and verify i8042 irq is removed as a
wake source
-`echo mem > /sys/power/state`. Press key and verify system wake
from i8042.
Cq-Depend: chromium:4891663
Change-Id: I7d093d94a666263684645ef724e945069c68c806
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 848fd93..49ff8dd 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -44,12 +44,10 @@
/*
* b/218874489 - This should really be ESPI_VW_IRQ_LEVEL_HIGH,
- * but eSPI gets configured in verstage which is in RO.
- * We have already locked RO for guybrush devices so we need
- * make it so x86 coreboot re-initializes the vw_irq_polarity.
- * This leaves another problem, verstage also runs in S0i3, but
- * we don't run any other x86 coreboot stages, so we need to
- * figure out a way to reset the eSPI polarity.
+ * but eSPI gets configured in verstage which is in RO, and the
+ * RO is already locked down. As a workaround, the EC fw has
+ * been modified to use active low signalling for the
+ * interrupts that require it.
*/
.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1),
}"
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
index 643c534..83a4b2f 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
@@ -63,6 +63,7 @@
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Level, ActiveLow, Shared) {1}
/* Enable EC sync interrupt */
#define EC_ENABLE_SYNC_IRQ_GPIO