drivers/intel/fsp2_0: Fix running on x86_64
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 14d9742..3cff8fa 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -31,6 +31,13 @@
if PLATFORM_USES_FSP2_0
+config PLATFORM_USES_FSP2_X86_32
+ bool
+ default y
+ help
+ The FSP 2.0 runs in x86_32 protected mode.
+ Once there's a x86_64 FSP this needs to default to n.
+
config HAVE_INTEL_FSP_REPO
bool
help
diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c
index a134fed..4f93666 100644
--- a/src/drivers/intel/fsp2_0/header_display.c
+++ b/src/drivers/intel/fsp2_0/header_display.c
@@ -19,24 +19,24 @@
printk(BIOS_SPEW, "Type: %s/%s\n",
(hdr->component_attribute & 1) ? "release" : "debug",
(hdr->component_attribute & 2) ? "official" : "test");
- printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n",
- hdr->image_id, hdr->image_base, hdr->image_size);
+ printk(BIOS_SPEW, "image ID: %s, base 0x%zx + 0x%zx\n",
+ hdr->image_id, (size_t)hdr->image_base, (size_t)hdr->image_size);
printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n",
- hdr->cfg_region_offset, hdr->cfg_region_size);
+ (size_t)hdr->cfg_region_offset, (size_t)hdr->cfg_region_size);
if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) {
printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n",
- hdr->memory_init_entry_offset);
+ (size_t)hdr->memory_init_entry_offset);
}
if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) {
printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n",
- hdr->silicon_init_entry_offset);
+ (size_t)hdr->silicon_init_entry_offset);
if (CONFIG(PLATFORM_USES_FSP2_2))
printk(BIOS_SPEW, "\tMultiPhaseSiInit offset 0x%zx\n",
- hdr->multi_phase_si_init_entry_offset);
+ (size_t)hdr->multi_phase_si_init_entry_offset);
printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n",
- hdr->notify_phase_entry_offset);
+ (size_t)hdr->notify_phase_entry_offset);
}
}
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index f237a37..aa9a435 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -4,6 +4,7 @@
#define _FSP2_0_INFO_HEADER_H_
#include <types.h>
+#include <commonlib/bsd/compiler.h>
#define FSP_HDR_OFFSET 0x94
#if CONFIG(PLATFORM_USES_FSP2_2)
@@ -16,24 +17,29 @@
#define FSP_HDR_ATTRIB_FSPM 2
#define FSP_HDR_ATTRIB_FSPS 3
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
struct fsp_header {
uint32_t fsp_revision;
- size_t image_size;
- uintptr_t image_base;
+ uint32_t image_size;
+ uint32_t image_base;
uint16_t image_attribute;
uint8_t spec_version;
uint16_t component_attribute;
- size_t cfg_region_offset;
- size_t cfg_region_size;
- size_t temp_ram_init_entry;
- size_t temp_ram_exit_entry;
- size_t notify_phase_entry_offset;
- size_t memory_init_entry_offset;
- size_t silicon_init_entry_offset;
- size_t multi_phase_si_init_entry_offset;
+ uint32_t cfg_region_offset;
+ uint32_t cfg_region_size;
+ uint32_t temp_ram_init_entry;
+ uint32_t temp_ram_exit_entry;
+ uint32_t notify_phase_entry_offset;
+ uint32_t memory_init_entry_offset;
+ uint32_t silicon_init_entry_offset;
+ uint32_t multi_phase_si_init_entry_offset;
char image_id[sizeof(uint64_t) + 1];
uint8_t revision;
-};
+} __packed;
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
+
enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 979cff3..827c95d 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -21,6 +21,7 @@
uint8_t Reserved[23];
} __packed;
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
struct FSPM_ARCH_UPD {
///
/// Revision of the structure. For FSP v2.0 value is 1.
@@ -31,12 +32,12 @@
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
- void *NvsBufferPtr;
+ uint32_t NvsBufferPtr;
///
/// Pointer to the temporary stack base address to be
/// consumed inside FspMemoryInit() API.
///
- void *StackBase;
+ uint32_t StackBase;
///
/// Temporary stack size to be consumed inside
/// FspMemoryInit() API.
@@ -53,7 +54,11 @@
uint32_t BootMode;
uint8_t Reserved1[8];
} __packed;
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
+#endif
struct FSPS_ARCH_UPD {
///
/// Revision of the structure. For FSP v2.2 value is 1.
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 92f3d9d..f2fcec4 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -87,7 +87,7 @@
void *data;
size_t mrc_size;
- arch_upd->NvsBufferPtr = NULL;
+ arch_upd->NvsBufferPtr = 0;
if (!CONFIG(CACHE_MRC_SETTINGS))
return;
@@ -101,7 +101,7 @@
return;
/* MRC cache found */
- arch_upd->NvsBufferPtr = data;
+ arch_upd->NvsBufferPtr = (uintptr_t)data;
printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size);
}
@@ -142,7 +142,7 @@
stack_end) != CB_SUCCESS)
return CB_ERR;
- arch_upd->StackBase = (void *)stack_begin;
+ arch_upd->StackBase = stack_begin;
return CB_SUCCESS;
}
@@ -159,7 +159,7 @@
* Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack.
*/
if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) {
- arch_upd->StackBase = temp_ram;
+ arch_upd->StackBase = (uintptr_t)temp_ram;
arch_upd->StackSize = sizeof(temp_ram);
} else if (setup_fsp_stack_frame(arch_upd, memmap)) {
return CB_ERR;
@@ -237,7 +237,7 @@
fsp_version = fsp_memory_settings_version(hdr);
- upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
+ upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
fsp_verify_upd_header_signature(upd->FspUpdHeader.Signature, FSPM_UPD_SIGNATURE);
@@ -289,12 +289,12 @@
post_code(POST_MEM_PREINIT_PREP_END);
/* Call FspMemoryInit */
- fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+ fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->memory_init_entry_offset);
fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
- if (ENV_X86_64)
+ if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
status = protected_mode_call_2arg(fsp_raminit,
(uintptr_t)&fspm_upd,
(uintptr_t)fsp_get_hob_list_ptr());
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 8a51c0b..cbccc6e 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -16,7 +16,7 @@
if (!fsps_hdr.notify_phase_entry_offset)
die("Notify_phase_entry_offset is zero!\n");
- fspnotify = (void *) (fsps_hdr.image_base +
+ fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base +
fsps_hdr.notify_phase_entry_offset);
fsp_before_debug_notify(fspnotify, ¬ify_params);
@@ -31,7 +31,7 @@
post_code(POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE);
}
- if (ENV_X86_64)
+ if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
ret = protected_mode_call_1arg(fspnotify, (uintptr_t)¬ify_params);
else
ret = fspnotify(¬ify_params);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 26ff59d..8572b24 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -86,7 +86,7 @@
struct fsp_multi_phase_params multi_phase_params;
struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
- supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
+ supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE);
@@ -110,14 +110,14 @@
logo_entry = soc_load_logo(upd);
/* Call SiliconInit */
- silicon_init = (void *) (hdr->image_base +
+ silicon_init = (void *) (uintptr_t)(hdr->image_base +
hdr->silicon_init_entry_offset);
fsp_debug_before_silicon_init(silicon_init, supd, upd);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
post_code(POST_FSP_SILICON_INIT);
- if (ENV_X86_64)
+ if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd);
else
status = silicon_init(upd);
@@ -145,7 +145,7 @@
return;
/* Call MultiPhaseSiInit */
- multi_phase_si_init = (void *) (hdr->image_base +
+ multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base +
hdr->multi_phase_si_init_entry_offset);
/* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */