mainboards: align on using ACPI_Sx definitions
The mainboard_smi_sleep() function takes ACPI sleep values
of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure
that whatever hardware PM1 control register values are used
the interface to the mainboard is the same. Move all the
SMI handlers in the mainboard directory to not open code
the literal values 3 and 5 for ACPI_S3 and ACPI_S5.
There were a few notable exceptions where the code was
attempting to use the hardware values and not the common
translated values. The few users of SLEEP_STATE_X were
updated to align with ACPI_SX as those defines are
already equal. The removal of SLEEP_STATE_X defines is
forthcoming in a subsequent patch.
BUG=chrome-os-partner:54977
Change-Id: I76592c9107778cce5995e5af764760453f54dc50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15664
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/intel/amenia/smihandler.c b/src/mainboard/intel/amenia/smihandler.c
index 3b855f2..edf8190 100644
--- a/src/mainboard/intel/amenia/smihandler.c
+++ b/src/mainboard/intel/amenia/smihandler.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <soc/pm.h>
@@ -25,12 +26,12 @@
return;
switch (slp_typ) {
- case 3:
+ case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
enable_gpe(GPIO_TIER_1_SCI);
break;
- case 5:
+ case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c
index b78dd67..229085d 100644
--- a/src/mainboard/intel/baskingridge/mainboard_smi.c
+++ b/src/mainboard/intel/baskingridge/mainboard_smi.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
@@ -33,11 +34,11 @@
u8 reg8;
switch (slp_typ) {
- case SLP_TYP_S3:
- case SLP_TYP_S4:
+ case ACPI_S3:
+ case ACPI_S4:
break;
- case SLP_TYP_S5:
+ case ACPI_S5:
/* Turn off LED */
reg8 = inb(SIO_GPIO_BASE_SET4);
reg8 |= (1 << 5);
diff --git a/src/mainboard/intel/cougar_canyon2/mainboard_smi.c b/src/mainboard/intel/cougar_canyon2/mainboard_smi.c
index db9d198..5edcf13 100644
--- a/src/mainboard/intel/cougar_canyon2/mainboard_smi.c
+++ b/src/mainboard/intel/cougar_canyon2/mainboard_smi.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
@@ -34,11 +35,11 @@
u8 reg8;
switch (slp_typ) {
- case SLP_TYP_S3:
- case SLP_TYP_S4:
+ case ACPI_S3:
+ case ACPI_S4:
break;
- case SLP_TYP_S5:
+ case ACPI_S5:
/* Turn off LED */
reg8 = inb(SIO_GPIO_BASE_SET4);
reg8 |= (1 << 5);
diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c
index ecc6dd3..3662e6e 100644
--- a/src/mainboard/intel/emeraldlake2/smihandler.c
+++ b/src/mainboard/intel/emeraldlake2/smihandler.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
@@ -33,11 +34,11 @@
u8 reg8;
switch (slp_typ) {
- case 3:
- case 4:
+ case ACPI_S3:
+ case ACPI_S4:
break;
- case 5:
+ case ACPI_S5:
/* Turn off LED */
reg8 = inb(SIO_GPIO_BASE_SET4);
reg8 |= (1 << 5);
diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c
index 4b903ea..9ddf8d0 100644
--- a/src/mainboard/intel/kunimitsu/smihandler.c
+++ b/src/mainboard/intel/kunimitsu/smihandler.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
@@ -84,11 +85,11 @@
{
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
switch (slp_typ) {
- case 3:
+ case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
- case 5:
+ case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
diff --git a/src/mainboard/intel/stargo2/mainboard_smi.c b/src/mainboard/intel/stargo2/mainboard_smi.c
index 014fa07..0e7e986 100644
--- a/src/mainboard/intel/stargo2/mainboard_smi.c
+++ b/src/mainboard/intel/stargo2/mainboard_smi.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
@@ -28,9 +29,9 @@
u8 reg8;
switch (slp_typ) {
- case SLP_TYP_S3:
- case SLP_TYP_S4:
- case SLP_TYP_S5:
+ case ACPI_S3:
+ case ACPI_S4:
+ case ACPI_S5:
break;
}
}
diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c
index 0f77bf3..6cd01e2 100644
--- a/src/mainboard/intel/strago/smihandler.c
+++ b/src/mainboard/intel/strago/smihandler.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <arch/acpi.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
@@ -100,7 +101,7 @@
{
/* Disable USB charging if required */
switch (slp_typ) {
- case 3:
+ case ACPI_S3:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
@@ -115,7 +116,7 @@
/* Enable wake pin in GPE block. */
enable_gpe(WAKE_GPIO_EN);
break;
- case 5:
+ case ACPI_S5:
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
@@ -140,7 +141,7 @@
;
/* Set LPC lines to low power in S3/S5. */
- if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5))
+ if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
lpc_set_low_power();
#endif
}