soc/intel: Rename IA common code module from `TOM` to `RAMTOP`
This patch renames all references of `top_of_ram` (TOM) in IA common
`basecode` module (for example: functions, variables, Kconfig,
Makefile and comments) with `ramtop` aka top_of_ram to make it more
meaningful and to avoid conflicts with Intel SA chipset TOM registers.
BUG=Able to build and boot google/rex with the same ~49ms savings
in place.
Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 4f0dbf6..6d25844 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -24,8 +24,8 @@
#include <types.h>
#include <vb2_api.h>
-#if CONFIG(SOC_INTEL_COMMON_BASECODE_TOM)
-#include <intelbasecode/tom.h>
+#if CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP)
+#include <intelbasecode/ramtop.h>
#endif
static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
@@ -259,10 +259,10 @@
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");
- /* Early caching of TOM region if valid mrc cache data is found */
-#if (CONFIG(SOC_INTEL_COMMON_BASECODE_TOM))
+ /* Early caching of RAMTOP region if valid mrc cache data is found */
+#if (CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP))
if (arch_upd->NvsBufferPtr)
- early_tom_enable_cache_range();
+ early_ramtop_enable_cache_range();
#endif
/* Give SoC and mainboard a chance to update the UPD */
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/ramtop.h b/src/soc/intel/common/basecode/include/intelbasecode/ramtop.h
new file mode 100644
index 0000000..067dd6b
--- /dev/null
+++ b/src/soc/intel/common/basecode/include/intelbasecode/ramtop.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_COMMON_BASECODE_RAMTOP_H
+#define SOC_INTEL_COMMON_BASECODE_RAMTOP_H
+
+#include <types.h>
+
+/* Early caching of top_of_ram region */
+void early_ramtop_enable_cache_range(void);
+
+/* Update the RAMTOP if required based on the input top_of_ram address */
+void update_ramtop(uint32_t addr);
+
+#endif
diff --git a/src/soc/intel/common/basecode/include/intelbasecode/tom.h b/src/soc/intel/common/basecode/include/intelbasecode/tom.h
deleted file mode 100644
index d78ecd1..0000000
--- a/src/soc/intel/common/basecode/include/intelbasecode/tom.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_COMMON_BASECODE_TOM_H
-#define SOC_INTEL_COMMON_BASECODE_TOM_H
-
-#include <types.h>
-
-/* Early caching of TOM region */
-void early_tom_enable_cache_range(void);
-
-/* Update the TOM if required based on the input TOM address */
-void update_tom(uint32_t addr);
-
-#endif
diff --git a/src/soc/intel/common/basecode/tom/Kconfig b/src/soc/intel/common/basecode/ramtop/Kconfig
similarity index 64%
rename from src/soc/intel/common/basecode/tom/Kconfig
rename to src/soc/intel/common/basecode/ramtop/Kconfig
index ff91725..2b600e7 100644
--- a/src/soc/intel/common/basecode/tom/Kconfig
+++ b/src/soc/intel/common/basecode/ramtop/Kconfig
@@ -1,15 +1,15 @@
-config SOC_INTEL_COMMON_BASECODE_TOM
+config SOC_INTEL_COMMON_BASECODE_RAMTOP
bool
default n
help
- Driver code to store the top_of_ram (TOM) address into
+ Driver code to store the top_of_ram (RAMTOP) address into
non-volatile space (CMOS) during the first boot and use
it across all consecutive boot.
- Purpose of this driver code is to cache the TOM (with a
+ Purpose of this driver code is to cache the RAMTOP (with a
fixed size) for all consecutive boots even before calling
into the FSP. Otherwise, this range remains un-cached until postcar
boot stage updates the MTRR programming. FSP-M and late romstage
- uses this uncached TOM range for various purposes and having the
+ uses this uncached RAMTOP range for various purposes and having the
ability to cache this range beforehand would help to optimize the boot
time (more than 50ms).
diff --git a/src/soc/intel/common/basecode/ramtop/Makefile.inc b/src/soc/intel/common/basecode/ramtop/Makefile.inc
new file mode 100644
index 0000000..4585173
--- /dev/null
+++ b/src/soc/intel/common/basecode/ramtop/Makefile.inc
@@ -0,0 +1,2 @@
+## SPDX-License-Identifier: GPL-2.0-only
+romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_RAMTOP) += ramtop.c
diff --git a/src/soc/intel/common/basecode/ramtop/ramtop.c b/src/soc/intel/common/basecode/ramtop/ramtop.c
new file mode 100644
index 0000000..89e84d9
--- /dev/null
+++ b/src/soc/intel/common/basecode/ramtop/ramtop.c
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <ip_checksum.h>
+#include <intelbasecode/ramtop.h>
+#include <pc80/mc146818rtc.h>
+#include <stdint.h>
+
+/* We need a region in CMOS to store the RAMTOP address */
+
+#define RAMTOP_SIGNATURE 0x52544F50 /* 'RTOP' */
+
+#define RAMTOP_CMOS_OFFSET 0x64
+
+/*
+ * Address of the ramtop_cmos_offset byte in CMOS. Should be reserved
+ * in mainboards' cmos.layout and not covered by checksum.
+ */
+
+#if CONFIG(USE_OPTION_TABLE)
+#include "option_table.h"
+#if CMOS_VSTART_ramtop_cmos_offset != RAMTOP_CMOS_OFFSET * 8
+#error "CMOS start for RAMTOP_CMOS is not correct, check your cmos.layout"
+#endif
+#if CMOS_VLEN_ramtop_cmos_offset != 12
+#error "CMOS length for RAMTOP_CMOS bytes are not correct, check your cmos.layout"
+#endif
+#endif
+
+struct ramtop_table {
+ uint32_t signature;
+ uint32_t addr;
+ uint16_t checksum;
+} __packed;
+
+/* Read and validate ramtop_table structure from CMOS */
+static int ramtop_cmos_read(struct ramtop_table *ramtop)
+{
+ u8 i, *p;
+ u16 csum;
+
+ for (p = (u8 *)ramtop, i = 0; i < sizeof(*ramtop); i++, p++)
+ *p = cmos_read(RAMTOP_CMOS_OFFSET + i);
+
+ /* Verify signature */
+ if (ramtop->signature != RAMTOP_SIGNATURE) {
+ printk(BIOS_DEBUG, "ramtop_table invalid signature\n");
+ return -1;
+ }
+
+ /* Verify checksum over signature and counter only */
+ csum = compute_ip_checksum(ramtop, offsetof(struct ramtop_table, checksum));
+
+ if (csum != ramtop->checksum) {
+ printk(BIOS_DEBUG, "ramtop_table checksum mismatch\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Write ramtop_table structure to CMOS */
+static void ramtop_cmos_write(struct ramtop_table *ramtop)
+{
+ u8 i, *p;
+
+ /* Checksum over signature and counter only */
+ ramtop->checksum = compute_ip_checksum(
+ ramtop, offsetof(struct ramtop_table, checksum));
+
+ for (p = (u8 *)ramtop, i = 0; i < sizeof(*ramtop); i++, p++)
+ cmos_write(*p, RAMTOP_CMOS_OFFSET + i);
+}
+
+/* Update the RAMTOP if required based on the input top_of_ram address */
+void update_ramtop(uint32_t addr)
+{
+ struct ramtop_table ramtop;
+
+ /* Read and update ramtop (if required) */
+ if (ramtop_cmos_read(&ramtop) < 0) {
+ /* Structure invalid, re-initialize */
+ ramtop.signature = RAMTOP_SIGNATURE;
+ ramtop.addr = 0;
+ }
+
+ /* Update ramtop if required */
+ if (ramtop.addr == addr)
+ return;
+
+ ramtop.addr = addr;
+
+ /* Write the new top_of_ram address to CMOS */
+ ramtop_cmos_write(&ramtop);
+
+ printk(BIOS_DEBUG, "Updated the RAMTOP address into CMOS 0x%x\n", ramtop.addr);
+}
+
+static uint32_t get_ramtop_addr(void)
+{
+ struct ramtop_table ramtop;
+
+ if (ramtop_cmos_read(&ramtop) < 0)
+ return 0;
+
+ return ramtop.addr;
+}
+
+/* Early caching of top_of_ram region */
+void early_ramtop_enable_cache_range(void)
+{
+ uint32_t ramtop = get_ramtop_addr();
+ if (!ramtop)
+ return;
+
+ int mtrr = get_free_var_mtrr();
+ if (mtrr == -1) {
+ printk(BIOS_WARNING, "ramtop_table update failure due to no free MTRR available!\n");
+ return;
+ }
+ /*
+ * We need to make sure late romstage (including FSP-M post mem) will be run
+ * cached. Caching 16MB below ramtop is a safe to cover late romstage.
+ */
+ set_var_mtrr(mtrr, ramtop - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
+}
diff --git a/src/soc/intel/common/basecode/tom/Makefile.inc b/src/soc/intel/common/basecode/tom/Makefile.inc
deleted file mode 100644
index 2ebf4bb..0000000
--- a/src/soc/intel/common/basecode/tom/Makefile.inc
+++ /dev/null
@@ -1,2 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-romstage-$(CONFIG_SOC_INTEL_COMMON_BASECODE_TOM) += tom.c
diff --git a/src/soc/intel/common/basecode/tom/tom.c b/src/soc/intel/common/basecode/tom/tom.c
deleted file mode 100644
index de696d5..0000000
--- a/src/soc/intel/common/basecode/tom/tom.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <console/console.h>
-#include <cpu/x86/mtrr.h>
-#include <ip_checksum.h>
-#include <intelbasecode/tom.h>
-#include <pc80/mc146818rtc.h>
-#include <stdint.h>
-
-/* We need a region in CMOS to store the TOM address */
-
-#define TOM_SIGNATURE 0x5F544F4D /* '_TOM' */
-
-#define TOM_CMOS_OFFSET 0x64
-
-/*
- * Address of the tom_cmos_offset byte in CMOS. Should be reserved
- * in mainboards' cmos.layout and not covered by checksum.
- */
-
-#if CONFIG(USE_OPTION_TABLE)
-#include "option_table.h"
-#if CMOS_VSTART_tom_cmos_offset != TOM_CMOS_OFFSET * 8
-#error "CMOS start for TOM_CMOS is not correct, check your cmos.layout"
-#endif
-#if CMOS_VLEN_tom_cmos_offset != 12
-#error "CMOS length for TOM_CMOS bytes are not correct, check your cmos.layout"
-#endif
-#endif
-
-struct tom_table {
- uint32_t signature;
- uint32_t addr;
- uint16_t checksum;
-} __packed;
-
-/* Read and validate tom_table structure from CMOS */
-static int tom_cmos_read(struct tom_table *tom)
-{
- u8 i, *p;
- u16 csum;
-
- for (p = (u8 *)tom, i = 0; i < sizeof(*tom); i++, p++)
- *p = cmos_read(TOM_CMOS_OFFSET + i);
-
- /* Verify signature */
- if (tom->signature != TOM_SIGNATURE) {
- printk(BIOS_DEBUG, "tom_table invalid signature\n");
- return -1;
- }
-
- /* Verify checksum over signature and counter only */
- csum = compute_ip_checksum(tom, offsetof(struct tom_table, checksum));
-
- if (csum != tom->checksum) {
- printk(BIOS_DEBUG, "tom_table checksum mismatch\n");
- return -1;
- }
-
- return 0;
-}
-
-/* Write tom_table structure to CMOS */
-static void tom_cmos_write(struct tom_table *tom)
-{
- u8 i, *p;
-
- /* Checksum over signature and counter only */
- tom->checksum = compute_ip_checksum(
- tom, offsetof(struct tom_table, checksum));
-
- for (p = (u8 *)tom, i = 0; i < sizeof(*tom); i++, p++)
- cmos_write(*p, TOM_CMOS_OFFSET + i);
-}
-
-/* Update the TOM if required based on the input TOM address */
-void update_tom(uint32_t addr)
-{
- struct tom_table tom;
-
- /* Read and increment boot count */
- if (tom_cmos_read(&tom) < 0) {
- /* Structure invalid, re-initialize */
- tom.signature = TOM_SIGNATURE;
- tom.addr = 0;
- }
-
- /* Update TOM if required */
- if (tom.addr == addr)
- return;
-
- tom.addr = addr;
-
- /* Write the new count to CMOS */
- tom_cmos_write(&tom);
-
- printk(BIOS_DEBUG, "Updated the TOM address into CMOS 0x%x\n", tom.addr);
-}
-
-static uint32_t get_tom_addr(void)
-{
- struct tom_table tom;
-
- if (tom_cmos_read(&tom) < 0)
- return 0;
-
- return tom.addr;
-}
-
-/* Early caching of TOM region */
-void early_tom_enable_cache_range(void)
-{
- uint32_t tom = get_tom_addr();
- if (!tom)
- return;
-
- int mtrr = get_free_var_mtrr();
- if (mtrr == -1) {
- printk(BIOS_WARNING, "tom_table update failure due to no free MTRR available!\n");
- return;
- }
- /*
- * We need to make sure late romstage (including FSP-M post mem) will be run
- * cached. Caching 16MB below TOM is a safe to cover late romstage.
- */
- set_var_mtrr(mtrr, tom - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
-}
diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
index 380974e..e82c696 100644
--- a/src/soc/intel/common/block/systemagent/memmap.c
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -6,7 +6,7 @@
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
-#include <intelbasecode/tom.h>
+#include <intelbasecode/ramtop.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/systemagent.h>
#include <types.h>
@@ -71,11 +71,11 @@
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
/*
- * Store the top_of_ram (TOM) into the CMOS if SOC_INTEL_COMMON_BASECODE_TOM
+ * Store the top_of_ram (ramtop) into the CMOS if SOC_INTEL_COMMON_BASECODE_RAMTOP
* config is enabled.
*/
- if (ENV_ROMSTAGE && CONFIG(SOC_INTEL_COMMON_BASECODE_TOM))
- update_tom(top_of_ram);
+ if (ENV_ROMSTAGE && CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP))
+ update_ramtop(top_of_ram);
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index b9b1df0..e114a67 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -84,7 +84,7 @@
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE
- select SOC_INTEL_COMMON_BASECODE_TOM
+ select SOC_INTEL_COMMON_BASECODE_RAMTOP
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET