sb,soc/intel: Address TCO SECOND_TO_STS name collision
Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.
In src/soc/intel/denverton_ns:
#define TCO2_STS_SECOND_TO 0x02
In soc/intel/baytrail,braswell:
#define SECOND_TO_STS (1 << 17)
Elsewehere
#define SECOND_TO_STS (1 << 1)
It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.
Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 0d8be7b..35649f6 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -623,7 +623,7 @@
#define TCO1_STS 0x64
#define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66
-#define SECOND_TO_STS (1 << 1)
+#define TCO2_STS_SECOND_TO (1 << 1)
#endif
#define ALT_GP_SMI_EN2 0x5c