nb/intel/i945: Clean up raminit coding style
Tested with BUILD_TIMELESS=1, Getac P470 does not change.
Change-Id: I17739a9663d809647c22c415a0998edb61c04484
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b5444d1..c668e79 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -53,7 +53,7 @@
u32 reg32;
reg32 = MCHBAR32(DCC);
- reg32 &= ~((3<<21) | (1<<20) | (1<<19) | (7 << 16));
+ reg32 &= ~((3 << 21) | (1 << 20) | (1 << 19) | (7 << 16));
reg32 |= command;
/* Also set Init Complete */
@@ -229,8 +229,8 @@
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2);
- if (reg8 & ((1<<7)|(1<<2))) {
- if (reg8 & (1<<2)) {
+ if (reg8 & ((1 << 7) | (1 << 2))) {
+ if (reg8 & (1 << 2)) {
printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
/* Write back clears bit 2 */
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
@@ -238,9 +238,9 @@
}
- if (reg8 & (1<<7)) {
+ if (reg8 & (1 << 7)) {
printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
- reg8 &= ~(1<<7);
+ reg8 &= ~(1 << 7);
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8);
do_reset = 1;
}
@@ -266,12 +266,12 @@
/* Validate self refresh config */
if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) ||
(sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) &&
- !(MCHBAR8(SLFRCS) & (1<<0))) {
+ !(MCHBAR8(SLFRCS) & (1 << 0))) {
do_reset = 1;
}
if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) ||
(sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) &&
- !(MCHBAR8(SLFRCS) & (1<<1))) {
+ !(MCHBAR8(SLFRCS) & (1 << 1))) {
do_reset = 1;
}
}
@@ -563,7 +563,7 @@
sysinfo->refresh = REFRESH_7_8US;
else
sysinfo->refresh = REFRESH_15_6US;
- printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
+ printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh ? "7.8us" : "15.6us");
}
/**
@@ -599,38 +599,38 @@
for (i = 0; i < DIMM_SOCKETS; i++) { /* Channel 0 */
switch (sysinfo->dimm[i]) {
case SYSINFO_DIMM_X16DS:
- c0dramw |= (0x0000) << 4*(i % 2);
+ c0dramw |= (0x0000) << 4 * (i % 2);
break;
case SYSINFO_DIMM_X8DS:
- c0dramw |= (0x0001) << 4*(i % 2);
+ c0dramw |= (0x0001) << 4 * (i % 2);
break;
case SYSINFO_DIMM_X16SS:
- c0dramw |= (0x0000) << 4*(i % 2);
+ c0dramw |= (0x0000) << 4 * (i % 2);
break;
case SYSINFO_DIMM_X8DDS:
- c0dramw |= (0x0005) << 4*(i % 2);
+ c0dramw |= (0x0005) << 4 * (i % 2);
break;
case SYSINFO_DIMM_NOT_POPULATED:
- c0dramw |= (0x0000) << 4*(i % 2);
+ c0dramw |= (0x0000) << 4 * (i % 2);
break;
}
}
for (i = DIMM_SOCKETS; i < idx * DIMM_SOCKETS; i++) { /* Channel 1 */
switch (sysinfo->dimm[i]) {
case SYSINFO_DIMM_X16DS:
- c1dramw |= (0x0000) << 4*(i % 2);
+ c1dramw |= (0x0000) << 4 * (i % 2);
break;
case SYSINFO_DIMM_X8DS:
- c1dramw |= (0x0010) << 4*(i % 2);
+ c1dramw |= (0x0010) << 4 * (i % 2);
break;
case SYSINFO_DIMM_X16SS:
- c1dramw |= (0x0000) << 4*(i % 2);
+ c1dramw |= (0x0000) << 4 * (i % 2);
break;
case SYSINFO_DIMM_X8DDS:
- c1dramw |= (0x0050) << 4*(i % 2);
+ c1dramw |= (0x0050) << 4 * (i % 2);
break;
case SYSINFO_DIMM_NOT_POPULATED:
- c1dramw |= (0x0000) << 4*(i % 2);
+ c1dramw |= (0x0000) << 4 * (i % 2);
break;
}
}
@@ -644,7 +644,7 @@
int i;
for (i = 0; i < 16; i++)
- MCHBAR32(offset+(i*4)) = slew_rate_table[i];
+ MCHBAR32(offset+(i * 4)) = slew_rate_table[i];
}
static const u32 dq2030[] = {
@@ -1248,9 +1248,9 @@
dra = (dra << 4) | dra;
if (i < DIMM_SOCKETS)
- dra0 |= (dra << (i*8));
+ dra0 |= (dra << (i * 8));
else
- dra1 |= (dra << ((i - DIMM_SOCKETS)*8));
+ dra1 |= (dra << ((i - DIMM_SOCKETS) * 8));
}
MCHBAR16(C0DRA0) = dra0;
@@ -1633,10 +1633,10 @@
voltage = VOLTAGE_1_05;
if (MCHBAR32(DFT_STRAP1) & (1 << 20))
voltage = VOLTAGE_1_50;
- printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05)?"1.05V":"1.5V");
+ printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05) ? "1.05V" : "1.5V");
/* Gate graphics hardware for frequency change */
- reg8 = (1<<3) | (1<<1); /* disable crclk, gate cdclk */
+ reg8 = (1 << 3) | (1 << 1); /* disable crclk, gate cdclk */
pci_write_config8(PCI_DEV(0, 2, 0), GCFC + 1, reg8);
/* Get graphics frequency capabilities */
@@ -2455,19 +2455,19 @@
cas = sysinfo->cas;
reg32 = MCHBAR32(C0ODT) & 0xfff00000;
- reg32 |= odt[(cas-3) * 2];
+ reg32 |= odt[(cas - 3) * 2];
MCHBAR32(C0ODT) = reg32;
reg32 = MCHBAR32(C1ODT) & 0xfff00000;
- reg32 |= odt[(cas-3) * 2];
+ reg32 |= odt[(cas - 3) * 2];
MCHBAR32(C1ODT) = reg32;
reg32 = MCHBAR32(C0ODT + 4) & 0x1fc8ffff;
- reg32 |= odt[((cas-3) * 2) + 1];
+ reg32 |= odt[((cas - 3) * 2) + 1];
MCHBAR32(C0ODT + 4) = reg32;
reg32 = MCHBAR32(C1ODT + 4) & 0x1fc8ffff;
- reg32 |= odt[((cas-3) * 2) + 1];
+ reg32 |= odt[((cas - 3) * 2) + 1];
MCHBAR32(C1ODT + 4) = reg32;
}
@@ -2485,16 +2485,16 @@
#define CLOCKS_WIDTH 3
#endif
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED)
- clocks[0] |= (1 << CLOCKS_WIDTH)-1;
+ clocks[0] |= (1 << CLOCKS_WIDTH) - 1;
if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
- clocks[0] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
+ clocks[0] |= ((1 << CLOCKS_WIDTH) - 1) << CLOCKS_WIDTH;
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED)
- clocks[1] |= (1 << CLOCKS_WIDTH)-1;
+ clocks[1] |= (1 << CLOCKS_WIDTH) - 1;
if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
- clocks[1] |= ((1 << CLOCKS_WIDTH)-1) << CLOCKS_WIDTH;
+ clocks[1] |= ((1 << CLOCKS_WIDTH) - 1) << CLOCKS_WIDTH;
#if CONFIG(OVERRIDE_CLOCK_DISABLE)
/* Usually system firmware turns off system memory clock signals to unused SO-DIMM slots
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 58fcfbc..ea37d9c 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -291,7 +291,7 @@
* It can be removed when the output message is not printed anymore
*/
if (MCHBAR8(C0WL0REOST + channel_offset) == 0)
- printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
+ printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset ? "1" : "0");
return 0;
}