mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0
This change adds fine-tuned USB2 PHY parameters for storo.
BUG=191089827
TEST=Built and verified USB2 eye diagram test result
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index bcd094b..7ddadbd 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -54,6 +54,15 @@
},
}"
+ register "usb2_ports[3]" = "{
+ .enable = 1,
+ .ocpin = OC_SKIP,
+ .tx_bias = USB2_BIAS_0MV,
+ .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
+ .pre_emp_bias = USB2_BIAS_28P15MV,
+ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
+ }" # WWAN
+
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,