tree d68f00bee66eb88ecdbbdb1e1849608d1279d1a8
parent 3db49929bd7d755aad920ae6b8757bba57864989
author Raul E Rangel <rrangel@chromium.org> 1617745282 -0600
committer Patrick Georgi <pgeorgi@google.com> 1617864502 +0000

soc/amd/common: Add PM_ESPI_INTR_CTRL

This register is used for masking/unmasking eSPI IRQs.

BUG=none
TEST=Build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>