amd/cimx/sb800: Fix building with clang
These are all set but unused variable problems.
Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
index a5d92ad..26d9110 100644
--- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
+++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c
@@ -101,8 +101,6 @@
IN UINT8 OpFlag
)
{
- UINT8 Temp;
- Temp = OpFlag;
RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
}
diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c
index 1d7d0f9..d9e1f13 100644
--- a/src/vendorcode/amd/cimx/sb800/AZALIA.c
+++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c
@@ -270,13 +270,11 @@
UINT8 dbTempVariable;
UINT16 dwTempVariable;
UINT32 ddBAR0;
- UINT32 ddTempVariable;
dbEnableAzalia = 0;
dbChannelNum = 0;
dbTempVariable = 0;
dwTempVariable = 0;
ddBAR0 = 0;
- ddTempVariable = 0;
if ( pConfig->AzaliaController == 1 ) {
return;
@@ -509,4 +507,3 @@
++tempAzaliaCodecEntryPtr;
}
}
-
diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
index 1c86c58..faec104 100644
--- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
+++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c
@@ -88,9 +88,6 @@
{
AGESA_STATUS Status;
- UINT64 tdValue;
- tdValue = 0x32314130384253ULL;
-
Status = AGESA_UNSUPPORTED;
saveConfigPointer (pConfig);
diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c
index 9e70e8b..c407537 100644
--- a/src/vendorcode/amd/cimx/sb800/EC.c
+++ b/src/vendorcode/amd/cimx/sb800/EC.c
@@ -109,8 +109,8 @@
IN AMDSBCFG* pConfig
)
{
- AMDSBCFG* pTmp; // dummy code
- pTmp = pConfig;
+ /* AMDSBCFG* pTmp; // dummy code */
+ /* pTmp = pConfig; */
}
/**
@@ -125,7 +125,7 @@
IN AMDSBCFG* pConfig
)
{
- AMDSBCFG* pTmp; // dummy code
- pTmp = pConfig;
+ /* AMDSBCFG* pTmp; // dummy code */
+ /* pTmp = pConfig; */
}
#endif
diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c
index d1715bc..ec2dd6e 100644
--- a/src/vendorcode/amd/cimx/sb800/GEC.c
+++ b/src/vendorcode/amd/cimx/sb800/GEC.c
@@ -137,9 +137,7 @@
IN AMDSBCFG* pConfig
)
{
- if ( !pConfig->GecConfig == 0) {
- return; //return if GEC controller is disabled.
- }
+ /* if ( !pConfig->GecConfig == 0) { */
+ /* return; //return if GEC controller is disabled. */
+ /* } */
}
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c
index 3d4ce82..149e1de 100644
--- a/src/vendorcode/amd/cimx/sb800/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c
@@ -330,14 +330,11 @@
UINT32 abValue;
UINT16 dwTempVar;
CPUID_DATA CpuId;
- UINT8 cimNativepciesupport;
UINT8 cimIrConfig;
UINT8 Data;
- cimNativepciesupport = (UINT8) pConfig->NativePcieSupport;
cimIrConfig = (UINT8) pConfig->IrConfig;
#if SB_CIMx_PARAMETER == 0
- cimNativepciesupport = cimNativepciesupportDefault;
cimIrConfig = cimIrConfigDefault;
#endif
@@ -518,8 +515,6 @@
UINT8 dbPortStatus;
UINT8 cimSpreadSpectrum;
UINT32 cimSpreadSpectrumType;
- AMDSBCFG* pTmp;
- pTmp = pConfig;
cimSpreadSpectrum = pConfig->SpreadSpectrum;
cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType;
@@ -606,13 +601,11 @@
{
UINT32 cimResetCpuOnSyncFlood;
ABTBLENTRY *pAbTblPtr;
- AMDSBCFG* Temp;
cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood;
#if SB_CIMx_PARAMETER == 0
cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault;
#endif
- Temp = pConfig;
if ( pConfig->SbPcieOrderRule ) {
pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]);
abcfgTbl (pAbTblPtr);
@@ -800,9 +793,7 @@
IN AMDSBCFG* pConfig
)
{
- AMDSBCFG* Temp;
UINT8 dbValue;
- Temp = pConfig;
//RPR C-State and VID/FID Change
dbValue = getNumberOfCpuCores ();
if (dbValue > 1) {
diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
index 0e10a2a..04716bc 100644
--- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c
+++ b/src/vendorcode/amd/cimx/sb800/SBMAIN.c
@@ -218,8 +218,6 @@
{
// Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
// recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
- AMDSBCFG* pTmp; //lx-dummy for /W4 build
- pTmp = pConfig;
// Disable Power Button SMI
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0);
@@ -250,5 +248,3 @@
return Result;
}
-
-
diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c
index ba6c8f0..ae1d779 100644
--- a/src/vendorcode/amd/cimx/sb800/SBPort.c
+++ b/src/vendorcode/amd/cimx/sb800/SBPort.c
@@ -141,14 +141,12 @@
UINT8 dbCg2WR;
UINT8 dbCg1Pll;
UINT8 cimNbSbGen2;
- UINT8 cimSataMode;
UINT8 cimSpiFastReadEnable;
UINT8 cimSpiFastReadSpeed;
UINT8 cimSioHwmPortEnable;
UINT8 SataPortNum;
cimNbSbGen2 = pConfig->NbSbGen2;
- cimSataMode = pConfig->SATAMODE.SataModeReg;
// Adding Fast Read Function support
if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) {
cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
diff --git a/src/vendorcode/amd/cimx/sb800/SMM.c b/src/vendorcode/amd/cimx/sb800/SMM.c
index 894ec2a..1d501e5 100644
--- a/src/vendorcode/amd/cimx/sb800/SMM.c
+++ b/src/vendorcode/amd/cimx/sb800/SMM.c
@@ -63,8 +63,6 @@
IN AMDSBCFG* pConfig
)
{
- AMDSBCFG* pTmp; //lx-dummy for /W4 build
- pTmp = pConfig;
}
/**
@@ -79,8 +77,3 @@
)
{
}
-
-
-
-
-