diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 151627d..1840a2b 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -84,7 +84,6 @@
 
 #define PCH_EHCI1_DEV		PCI_DEV(0, 0x1d, 0)
 #define PCH_EHCI2_DEV		PCI_DEV(0, 0x1a, 0)
-#define PCH_XHCI_DEV		PCI_DEV(0, 0x14, 0)
 #define PCH_ME_DEV		PCI_DEV(0, 0x16, 0)
 #define PCH_PCIE_DEV_SLOT	28
 #define PCH_IOAPIC_PCI_BUS	250
@@ -92,6 +91,14 @@
 #define PCH_HPET_PCI_BUS	250
 #define PCH_HPET_PCI_SLOT	15
 
+/* PCI Configuration Space (D20:F0): xHCI */
+#define PCH_XHCI_DEV		PCI_DEV(0, 0x14, 0)
+
+#define XHCI_PWR_CNTL_STS	0x74
+
+/* xHCI memory base registers */
+#define XHCI_PORTSC_x_USB3(port)	(0x4c0 + (port) * 0x10)
+
 /* PCI Configuration Space (D31:F0): LPC */
 #define PCH_LPC_DEV		PCI_DEV(0, 0x1f, 0)
 #define SERIRQ_CNTL		0x64