mb/google/brya/var/dochi: Update overridetree
Update overridetree base on schematics revision 20230923.
BUG=b:299284564, b:298328847, b:299570339
TEST=emerge-brya coreboot
Change-Id: I0aff94ef3233fbc4f52d33bb2dc1285b4fe473f9
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78212
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 7ec2ce8..40d2866 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -495,6 +495,8 @@
config BOARD_GOOGLE_DOCHI
select BOARD_GOOGLE_BASEBOARD_BRYA
select SOC_INTEL_RAPTORLAKE
+ select DRIVERS_INTEL_ISH
+ select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
if BOARD_GOOGLE_BRYA_COMMON
diff --git a/src/mainboard/google/brya/variants/dochi/Makefile.inc b/src/mainboard/google/brya/variants/dochi/Makefile.inc
index defb592..9933121 100644
--- a/src/mainboard/google/brya/variants/dochi/Makefile.inc
+++ b/src/mainboard/google/brya/variants/dochi/Makefile.inc
@@ -5,3 +5,5 @@
romstage-y += memory.c
ramstage-y += gpio.c
+ramstage-$(CONFIG_FW_CONFIG) += variant.c
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
diff --git a/src/mainboard/google/brya/variants/dochi/fw_config.c b/src/mainboard/google/brya/variants/dochi/fw_config.c
new file mode 100644
index 0000000..d294707
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dochi/fw_config.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <console/console.h>
+#include <fw_config.h>
+#include <gpio.h>
+
+static const struct pad_config fp_disable_pads[] = {
+ PAD_NC(GPP_D0, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
+ PAD_NC(GPP_D1, NONE), /* D1 : ISH_GP1 ==> FP_RST_ODL */
+ PAD_NC(GPP_D2, NONE), /* D2 : ISH_GP2 ==> EN_FP_PWR */
+};
+
+static void fw_config_handle(void *unused)
+{
+ if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED))) {
+ printk(BIOS_INFO, "Disabling FP pads\n");
+ gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads));
+ }
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brya/variants/dochi/overridetree.cb b/src/mainboard/google/brya/variants/dochi/overridetree.cb
index 4f2c04a..2c3a513 100644
--- a/src/mainboard/google/brya/variants/dochi/overridetree.cb
+++ b/src/mainboard/google/brya/variants/dochi/overridetree.cb
@@ -1,6 +1,370 @@
+fw_config
+ field FPMCU_MASK 10
+ option FPMCU_DISABLED 0
+ option FPMCU_ENABLED 1
+ end
+ field STORAGE 30 31
+ option STORAGE_UNKNOWN 0
+ option STORAGE_UFS 1
+ option STORAGE_NVME 2
+ end
+end
chip soc/intel/alderlake
+ register "sagv" = "SaGv_Enabled"
+
+ # As per Intel Advisory doc#723158, the change is required to prevent possible
+ # display flickering issue.
+ register "disable_dynamic_tccold_handshake" = "true"
+
+ # SOC Aux orientation override:
+ # This is a bitfield that corresponds to up to 4 TCSS ports.
+ # Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2.
+ # TcssAuxOri = 0101b
+ # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports, otherwise is "0"
+ # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
+ # motherboard to USBC connector
+ register "tcss_aux_ori" = "0x5"
+ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
+ register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
+
+ register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 3
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
+
+ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3/2 Type A port3
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN
+
+ # FIVR configurations are disabled since the board doesn't have V1p05 and Vnn
+ # bypass rails implemented.
+ register "ext_fivr_settings" = "{
+ .configure_ext_fivr = 1,
+ }"
+
+ # Enable the Cnvi BT Audio Offload
+ register "cnvi_bt_audio_offload" = "1"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C3 | TouchScreen |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 550,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 550,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
device domain 0 on
+ device ref tbt_pcie_rp0 off end
+ device ref tbt_pcie_rp1 off end
+ device ref tbt_pcie_rp2 off end
+ device ref tcss_dma0 off end
+ device ref tcss_dma1 off end
+ device ref igpu on
+ chip drivers/gfx/generic
+ register "device_count" = "6"
+ # DDIA for eDP
+ register "device[0].name" = ""LCD""
+ # DDIB for HDMI
+ register "device[1].name" = ""DD01""
+ # TCP0 (DP-1) for port C0
+ register "device[2].name" = ""DD02""
+ register "device[2].use_pld" = "true"
+ register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
+ register "device[3].name" = ""DD03""
+ # TCP2 (DP-3) for port C1
+ register "device[4].name" = ""DD04""
+ register "device[4].use_pld" = "true"
+ register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
+ register "device[5].name" = ""DD05""
+ device generic 0 on end
+ end
+ end # Integrated Graphics Device
+ device ref dtt on
+ chip drivers/intel/dptf
+ ## sensor information
+ register "options.tsr[0].desc" = ""DRAM""
+ register "options.tsr[1].desc" = ""Soc""
+ register "options.tsr[2].desc" = ""Charger""
+
+ # TODO: below values are initial reference values only
+ ## Active Policy
+ register "policies.active" = "{
+ [0] = {
+ .target = DPTF_CPU,
+ .thresholds = {
+ TEMP_PCT(85, 90),
+ TEMP_PCT(75, 80),
+ TEMP_PCT(68, 70),
+ TEMP_PCT(62, 60),
+ TEMP_PCT(55, 50),
+ TEMP_PCT(50, 40),
+ TEMP_PCT(40, 30),
+ }
+ },
+ [1] = {
+ .target = DPTF_TEMP_SENSOR_1,
+ .thresholds = {
+ TEMP_PCT(60, 90),
+ TEMP_PCT(55, 80),
+ TEMP_PCT(52, 70),
+ TEMP_PCT(48, 60),
+ TEMP_PCT(44, 50),
+ TEMP_PCT(40, 40),
+ TEMP_PCT(36, 30),
+ }
+ }
+ }"
+
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 90, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 55, 5000),
+ [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 5000),
+ [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 55, 5000),
+ }"
+
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
+ }"
+
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 18000,
+ .max_power = 28000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,
+ },
+ .pl2 = {
+ .min_power = 40000,
+ .max_power = 40000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,
+ }
+ }"
+
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 1700 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }
+ }"
+
+ ## Fan Performance Control (Percent, Speed, Noise, Power)
+ register "controls.fan_perf" = "{
+ [0] = { 90, 6700, 220, 2200, },
+ [1] = { 80, 5800, 180, 1800, },
+ [2] = { 70, 5000, 145, 1450, },
+ [3] = { 60, 4900, 115, 1150, },
+ [4] = { 50, 3838, 90, 900, },
+ [5] = { 40, 2904, 55, 550, },
+ [6] = { 30, 2337, 30, 300, },
+ [7] = { 20, 1608, 15, 150, },
+ [8] = { 10, 800, 10, 100, },
+ [9] = { 0, 0, 0, 50, }
+ }"
+
+ ## Fan options
+ register "options.fan.fine_grained_control" = "1"
+ register "options.fan.step_size" = "2"
+
+ device generic 0 alias dptf_policy on end
+ end
+ end
+ device ref pcie4_0 on
+ # Enable CPU PCIE RP 1 using CLK 0
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 0,
+ .clk_src = 0,
+ .flags = PCIE_RP_LTR | PCIE_RP_AER,
+ }"
+ probe STORAGE STORAGE_UNKNOWN
+ probe STORAGE STORAGE_NVME
+ end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp8 off end
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end
+ device ref i2c0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5650""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5650""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-mode""
+ register "property_list[0].integer" = "2"
+ device i2c 1a on end
+ end
+ end # I2C0
+ device ref i2c1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+ device i2c 50 on end
+ end
+ end
+ device ref gspi1 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+ register "wake" = "GPE0_DW2_15"
+ register "has_power_resource" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
+ register "enable_delay_ms" = "3"
+ device spi 0 on
+ probe FPMCU_MASK FPMCU_ENABLED
+ end
+ end # FPMCU
+ end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref ish on
+ chip drivers/intel/ish
+ register "add_acpi_dma_property" = "true"
+ device generic 0 on end
+ end
+ probe STORAGE STORAGE_UNKNOWN
+ probe STORAGE STORAGE_UFS
+ end
+ device ref ufs on
+ probe STORAGE STORAGE_UNKNOWN
+ probe STORAGE STORAGE_UFS
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C1 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ register "usb_lpm_incapable" = "true"
+ device ref tcss_usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C1 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Camera""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port6 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A0 (DB)""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ device ref usb2_port9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ register "reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
+ device ref usb2_port10 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A0 (DB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ device ref usb3_port1 on end
+ end
+ end
+ end
+ end
end
end
diff --git a/src/mainboard/google/brya/variants/dochi/variant.c b/src/mainboard/google/brya/variants/dochi/variant.c
new file mode 100644
index 0000000..ae84884
--- /dev/null
+++ b/src/mainboard/google/brya/variants/dochi/variant.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <fw_config.h>
+#include <baseboard/variants.h>
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+ if (fw_config_probe(FW_CONFIG(FPMCU_MASK, FPMCU_DISABLED)))
+ config->serial_io_gspi_mode[PchSerialIoIndexGSPI1] = PchSerialIoDisabled;
+}