commit 2f58a007a7528090454d3384bacc973c503b4d20
author Elyes HAOUAS <ehaouas@noos.fr> Wed Apr 22 16:07:39 2020 +0200
committer Michał Żygowski <michal.zygowski@3mdeb.com> Mon Apr 27 11:32:49 2020 +0000
tree a0fa9210d72cb60d84b64d5def10a58150ed4903
parent db4f3bacce835222e53dea91976b15abc2113779

sb/pi/hudson: Const'ify pci_devfn_t devices

Change-Id: I9e63c811c4ac5674b2930304455d828ee516b521
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/southbridge/amd/pi/hudson/early_setup.c

diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 126a85c..b214ade 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -92,10 +92,9 @@
 void hudson_lpc_port80(void)
 {
 	u8 byte;
-	pci_devfn_t dev;
 
 	/* Enable port 80 LPC decode in pci function 3 configuration space. */
-	dev = PCI_DEV(0, 0x14, 3);
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	byte = pci_read_config8(dev, 0x4a);
 	byte |= 1 << 5; /* enable port 80 */
 	pci_write_config8(dev, 0x4a, byte);
@@ -103,13 +102,12 @@
 
 void hudson_lpc_decode(void)
 {
-	pci_devfn_t dev;
 	u32 tmp;
 
 	/* Enable LPC controller */
 	pm_write8(0xec, pm_read8(0xec) | 0x01);
 
-	dev = PCI_DEV(0, 0x14, 3);
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 	/* Serial port numeration on Hudson:
 	 * PORT0 - 0x3f8
 	 * PORT1 - 0x2f8
@@ -134,7 +132,7 @@
 		LPC_ALT_WIDEIO1_ENABLE,
 		LPC_ALT_WIDEIO2_ENABLE
 	};
-	pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+	const pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
 	uint32_t tmp;
 
 	/* Only allow port 0-2 */
@@ -168,7 +166,7 @@
  */
 static void lpc_wideio_window(uint16_t base, uint16_t size)
 {
-	pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
+	const pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC);
 	u32 tmp;
 
 	/* Support 512 or 16 bytes per range */
@@ -227,7 +225,7 @@
 static uintptr_t hudson_spibase(void)
 {
 	/* Make sure the base address is predictable */
-	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
 
 	u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER)
 							& 0xfffffff0;
@@ -280,7 +278,7 @@
 
 void hudson_tpm_decode_spi(void)
 {
-	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);	/* LPC device */
+	const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);	/* LPC device */
 
 	u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER);
 	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase