soc/intel/common: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index b9638fe..38e96ee 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -69,7 +69,7 @@
/* Prepare early base address for access before memory */
base = dw_i2c_get_soc_early_base(bus);
pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
- pci_write_config32(dev, PCI_COMMAND,
+ pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Take device out of reset */