nb/intel/haswell: Use new fixed BAR accessors
There are some cases in `northbridge_topology_init` where condensing the
operation using one macro changes the binary, and have been left as-is.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I59c7d1f8d816b95e86d39dcbf7bc7ce8c34f0770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51865
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index ff2456b..5f74a89 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -70,10 +70,10 @@
{
int i;
- const u32 addr_decoder_common = MCHBAR32(MAD_CHNL);
+ const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
- (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
+ (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
(addr_decoder_common >> 0) & 3,
@@ -81,7 +81,7 @@
(addr_decoder_common >> 4) & 3);
for (i = 0; i < NUM_CHANNELS; i++) {
- const u32 ch_conf = MCHBAR32(MAD_DIMM(i));
+ const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
@@ -164,7 +164,7 @@
}
/* Print the MRC version after executing the UEFI PEI stage */
- u32 version = MCHBAR32(MRC_REVISION);
+ u32 version = mchbar_read32(MRC_REVISION);
printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
(version >> 24) & 0xff, (version >> 16) & 0xff,
(version >> 8) & 0xff, (version >> 0) & 0xff);
@@ -234,10 +234,10 @@
memset(mem_info, 0, sizeof(struct memory_info));
- const u32 ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
+ const u32 ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
for (ch = 0; ch < NUM_CHANNELS; ch++) {
- const u32 ch_conf = MCHBAR32(MAD_DIMM(ch));
+ const u32 ch_conf = mchbar_read32(MAD_DIMM(ch));
/* DIMMs A/B */
for (d_num = 0; d_num < NUM_SLOTS; d_num++) {
const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256;