haswell: relocate `romstage_common` to northbridge
Other platforms do this as well. It will ease refactoring on follow-ups.
Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
index aebeed4..b93b911 100644
--- a/src/cpu/intel/haswell/Makefile.inc
+++ b/src/cpu/intel/haswell/Makefile.inc
@@ -1,5 +1,4 @@
ramstage-y += haswell_init.c
-romstage-y += romstage.c
romstage-y += ../car/romstage.c
ramstage-y += acpi.c
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 7906b83..b336e4c 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -118,16 +118,6 @@
# error "CONFIG_IED_REGION_SIZE is not a power of 2"
#endif
-struct pei_data;
-struct rcba_config_instruction;
-struct romstage_params {
- struct pei_data *pei_data;
- const void *gpio_map;
- const struct rcba_config_instruction *rcba_config;
- void (*copy_spd)(struct pei_data *);
-};
-void romstage_common(const struct romstage_params *params);
-
/* Lock MSRs */
void intel_cpu_haswell_finalize_smm(void);
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 8ef3079..b2fd530 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -14,6 +14,7 @@
romstage-y += memmap.c
romstage-y += raminit.c
+romstage-y += romstage.c
romstage-y += early_init.c
romstage-y += report_platform.c
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index c393049..b98d880 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -189,6 +189,16 @@
void intel_northbridge_haswell_finalize_smm(void);
+struct pei_data;
+struct rcba_config_instruction;
+struct romstage_params {
+ struct pei_data *pei_data;
+ const void *gpio_map;
+ const struct rcba_config_instruction *rcba_config;
+ void (*copy_spd)(struct pei_data *peid);
+};
+void romstage_common(const struct romstage_params *params);
+
void haswell_early_initialization(void);
void haswell_late_initialization(void);
void set_translation_table(int start, int end, u64 base, int inc);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
similarity index 97%
rename from src/cpu/intel/haswell/romstage.c
rename to src/northbridge/intel/haswell/romstage.c
index 7886de0..579eca7 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -7,11 +7,11 @@
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <romstage_handoff.h>
+#include <cpu/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/me.h>
-#include "haswell.h"
void romstage_common(const struct romstage_params *params)
{