cpu/amd/pi/00630F01: Remove unused directory and code
No board currently uses AMD PI 00630F01 so remove it.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If270c2a979346029748230952caba78a5e763d75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig
deleted file mode 100644
index c14cd54..0000000
--- a/src/cpu/amd/pi/00630F01/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config CPU_AMD_PI_00630F01
- bool
- select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_PI_00630F01
-
-config CPU_ADDR_BITS
- int
- default 48
-
-endif
diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc
deleted file mode 100644
index b2225b8..0000000
--- a/src/cpu/amd/pi/00630F01/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-romstage-y += fixme.c
-
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_15_init.c
-
-smm-y += udelay.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../smm
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl
deleted file mode 100644
index ede5021..0000000
--- a/src/cpu/amd/pi/00630F01/acpi/cpu.asl
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Processor Object
- *
- */
-Scope (\_SB) { /* define processor scope */
-
- Device (P000) {
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- }
-
- Device (P001) {
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- }
-
- Device (P002) {
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- }
-
- Device (P003) {
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- }
-
- Device (P004) {
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- }
-
- Device (P005) {
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- }
-
- Device (P006) {
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- }
-
- Device (P007) {
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- }
-} /* End _SB scope */
diff --git a/src/cpu/amd/pi/00630F01/chip_name.c b/src/cpu/amd/pi/00630F01/chip_name.c
deleted file mode 100644
index fabafe6..0000000
--- a/src/cpu/amd/pi/00630F01/chip_name.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_pi_00630F01_ops = {
- CHIP_NAME("AMD CPU Family 15h Model 30h-3Fh")
-};
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
deleted file mode 100644
index 645b588..0000000
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <Porting.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-void amd_initcpuio(void)
-{
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
-
- /* Enable legacy video routing: D18F1xF4 VGA Enable */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
- PciData = 1;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* The platform BIOS needs to ensure the memory ranges of Hudson legacy
- * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
- * set to non-posted regions.
- */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
- /* last address before processor local APIC at FEE00000 */
- PciData = 0x00FEDF00;
- /* set NP (non-posted) bit */
- PciData |= 1 << 7;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
- /* lowest NP address is HPET at FED00000 */
- PciData = (0xFED00000 >> 8) | 3;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Map the remaining PCI hole as posted MMIO */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
- /* last address before non-posted range */
- PciData = 0x00FECF00;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
- MsrReg = (MsrReg >> 8) | 3;
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
- PciData = (UINT32)MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
- /* Send all IO (0000-FFFF) to southbridge. */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
- PciData = 0x0000F000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
- PciData = 0x00000003;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
deleted file mode 100644
index 31d9430..0000000
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/smm.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-
-static void model_15_init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Model 15 Init.\n");
-
- u8 i;
- msr_t msr;
- int num_banks;
- int msrno;
- unsigned int cpu_idx;
-#if CONFIG(LOGICAL_CPUS)
- u32 siblings;
-#endif
-
- disable_cache();
- /* Enable access to AMD RdDram and WrDram extension bits */
- msr = rdmsr(SYSCFG_MSR);
- msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- /*
- * BSP: make a0000-bffff UC, c0000-fffff WB,
- * same as OntarioApMtrrSettingsList for APs
- */
- msr.lo = msr.hi = 0;
- wrmsr(MTRR_FIX_16K_A0000, msr);
- msr.lo = msr.hi = 0x1e1e1e1e;
- wrmsr(MTRR_FIX_64K_00000, msr);
- wrmsr(MTRR_FIX_16K_80000, msr);
- for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
- wrmsr(msrno, msr);
-
- msr = rdmsr(SYSCFG_MSR);
- msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
- msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
- wrmsr(SYSCFG_MSR, msr);
-
- x86_mtrr_check();
- x86_enable_cache();
-
- /* zero the machine check error status registers */
- msr = rdmsr(IA32_MCG_CAP);
- num_banks = msr.lo & MCA_BANKS_MASK;
- msr.lo = 0;
- msr.hi = 0;
- for (i = 0; i < num_banks; i++)
- wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-
- /* Enable the local CPU APICs */
- setup_lapic();
-
-#if CONFIG(LOGICAL_CPUS)
- siblings = cpuid_ecx(0x80000008) & 0xff;
-
- if (siblings > 0) {
- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1 << (33 - 32);
- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
- /* DisableCf8ExtCfg */
- msr = rdmsr(NB_CFG_MSR);
- msr.hi &= ~(1 << (46 - 32));
- wrmsr(NB_CFG_MSR, msr);
-
- if (CONFIG(HAVE_SMI_HANDLER)) {
- cpu_idx = cpu_info()->index;
- printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
-
- /* Set SMM base address for this CPU */
- msr = rdmsr(SMM_BASE_MSR);
- msr.lo = SMM_BASE - (cpu_idx * 0x400);
- wrmsr(SMM_BASE_MSR, msr);
-
- /* Enable the SMM memory window */
- msr = rdmsr(SMM_MASK_MSR);
- msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
- wrmsr(SMM_MASK_MSR, msr);
- }
-
- /* Write protect SMM space with SMMLOCK. */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (1 << 0);
- wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
- .init = model_15_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0x630f00 }, /* KV-A0 */
- { X86_VENDOR_AMD, 0x630f01 }, /* KV-A1 */
- { 0, 0 },
-};
-
-static const struct cpu_driver model_15 __cpu_driver = {
- .ops = &cpu_dev_ops,
- .id_table = cpu_table,
-};
diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c
deleted file mode 100644
index c09dde9..0000000
--- a/src/cpu/amd/pi/00630F01/udelay.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * udelay() implementation for SMI handlers
- * This is neat in that it never writes to hardware registers, and thus does not
- * modify the state of the hardware while servicing SMIs.
- */
-
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/tsc.h>
-#include <delay.h>
-#include <stdint.h>
-
-void udelay(uint32_t us)
-{
- uint8_t fid, did, pstate_idx;
- uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
- msr_t msr;
- const uint64_t tsc_base = 100000000;
-
- /* Get initial timestamp before we do the math */
- tsc_start = rdtscll();
-
- /* Get the P-state. This determines which MSR to read */
- msr = rdmsr(PS_STS_REG);
- pstate_idx = msr.lo & 0x07;
-
- /* Get FID and VID for current P-State */
- msr = rdmsr(PSTATE_0_MSR + pstate_idx);
-
- /* Extract the FID and VID values */
- fid = msr.lo & 0x3f;
- did = (msr.lo >> 6) & 0x7;
-
- /* Calculate the CPU clock (from base freq of 100MHz) */
- tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
-
- /* Now go on and wait */
- tsc_wait_ticks = (tsc_clock / 1000000) * us;
-
- do {
- tsc_now = rdtscll();
- } while (tsc_now - tsc_wait_ticks < tsc_start);
-}
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
index 7b214f7..05d1065 100644
--- a/src/cpu/amd/pi/Kconfig
+++ b/src/cpu/amd/pi/Kconfig
@@ -2,7 +2,6 @@
config CPU_AMD_PI
bool
- default y if CPU_AMD_PI_00630F01
default y if CPU_AMD_PI_00730F01
default n
select ARCH_ALL_STAGES_X86_32
@@ -38,5 +37,4 @@
endif # CPU_AMD_PI
-source "src/cpu/amd/pi/00630F01/Kconfig"
source "src/cpu/amd/pi/00730F01/Kconfig"
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index dc9fd6b..ae04253 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -1,4 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
-subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01