soc/apollolake: Make IO decode / enable register configurable
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index fe0cb93..00c47f3 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -17,6 +17,7 @@
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/gpio.h>
+#include <soc/soc_chip.h>
#include <soc/systemagent.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -82,8 +83,24 @@
/* Prepare UART for serial console. */
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
uart_bootblock_init();
- if (CONFIG(DRIVERS_UART_8250IO))
- lpc_io_setup_comm_a_b();
+
+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+ LPC_IOE_EC_62_66;
+
+ const config_t *config = config_of_soc();
+
+
+ if (config->lpc_ioe) {
+ io_enables = config->lpc_ioe & 0x3f0f;
+ lpc_set_fixed_io_ranges(config->lpc_iod, 0x1377);
+ } else {
+ /* IO Decode Range */
+ if (CONFIG(DRIVERS_UART_8250IO))
+ lpc_io_setup_comm_a_b();
+ }
+
+ /* IO Decode Enable */
+ lpc_enable_fixed_io_ranges(io_enables);
if (CONFIG(TPM_ON_FAST_SPI))
tpm_enable();
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index f531381..0073103 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -106,6 +106,10 @@
uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */
+ /* LPC fixed enables and ranges */
+ uint16_t lpc_iod;
+ uint16_t lpc_ioe;
+
/* Configure LPSS S0ix Enable */
uint8_t lpss_s0ix_enable;