mb/lenovo/w541: Add ThinkPad W541
Add support for the ThinkPad W541 based on Peter Lemenkov's initial W541
port. Compiled and tested with SeaBIOS and Tianocore booting into Arch
Linux 5.10.32-lts. The Haswell mrc.bin blob is required.
Tested working:
- SATA SSD
- SATA DVD drive
- M.2 SATA
- All USB ports
- SD card reader
- Speakers/headphone jack
- Keyboard/touchpad
- libgfxinit
- VGA
- mini DisplayPort (Thunderbolt untested)
- eDP laptop screen
- NVIDIA GPU in Linux
- Camera/Mic
- Smartcard reader
- Internal flashing when IFD is unlocked
- ThinkPad basic dock (VGA, USB, Ethernet)
- CMOS options
- WLAN
- Bluetooth
- Ethernet
- Using me_cleaner
- All DDR3 slots
Not working:
- Keyboard backlight
- First boot can take up to 20s (MRC.bin is slow)
Untested:
- Thunderbolt
- Internal flashing when IFD is locked
- Other ThinkPad docks (DisplayPort, DVI, Audio)
- ExpressCard slot
- Battery thresholds
- WWAN card
- Fingerprint reader
- USB Debug console
Signed-off-by: Justin Wu <amersel@runbox.me>
Change-Id: Ia43070f51bba3cf59ba9b7d9e29e4e778efbeb08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52659
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/lenovo/w541/Kconfig b/src/mainboard/lenovo/w541/Kconfig
new file mode 100644
index 0000000..efa3a12
--- /dev/null
+++ b/src/mainboard/lenovo/w541/Kconfig
@@ -0,0 +1,49 @@
+if BOARD_LENOVO_THINKPAD_W541
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_LENOVO_H8
+ select EC_LENOVO_PMH7
+ select H8_HAS_BAT_TRESHOLDS_IMPL
+ select H8_HAS_PRIMARY_FN_KEYS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM1
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_HASWELL
+ select NO_UART_ON_SUPERIO
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_LYNXPOINT
+ select SYSTEM_TYPE_LAPTOP
+
+config GFX_GMA_PANEL_1_PORT
+ default "DP3"
+
+config MAINBOARD_DIR
+ string
+ default "lenovo/w541"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "ThinkPad W541"
+
+config DRIVER_LENOVO_SERIALS
+ bool
+ default n
+
+config PS2K_EISAID
+ default "LEN0071"
+
+config PS2M_EISAID
+ default "LEN004A"
+
+config THINKPADEC_HKEY_EISAID
+ default "LEN0068"
+
+endif
diff --git a/src/mainboard/lenovo/w541/Kconfig.name b/src/mainboard/lenovo/w541/Kconfig.name
new file mode 100644
index 0000000..f2ee59c
--- /dev/null
+++ b/src/mainboard/lenovo/w541/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_LENOVO_THINKPAD_W541
+ bool "ThinkPad W541"
diff --git a/src/mainboard/lenovo/w541/Makefile.inc b/src/mainboard/lenovo/w541/Makefile.inc
new file mode 100644
index 0000000..ebe01ae
--- /dev/null
+++ b/src/mainboard/lenovo/w541/Makefile.inc
@@ -0,0 +1,2 @@
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/w541/acpi/ec.asl b/src/mainboard/lenovo/w541/acpi/ec.asl
new file mode 100644
index 0000000..8dea152
--- /dev/null
+++ b/src/mainboard/lenovo/w541/acpi/ec.asl
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/w541/acpi/platform.asl b/src/mainboard/lenovo/w541/acpi/platform.asl
new file mode 100644
index 0000000..f5a4df7
--- /dev/null
+++ b/src/mainboard/lenovo/w541/acpi/platform.asl
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+Method(_WAK,1)
+{
+ /* ME may not be up yet. */
+ \_TZ.MEB1 = 0
+ \_TZ.MEB2 = 0
+ Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+ \_SB.PCI0.LPCB.EC.RADI(0)
+}
diff --git a/src/mainboard/lenovo/w541/acpi/superio.asl b/src/mainboard/lenovo/w541/acpi/superio.asl
new file mode 100644
index 0000000..ee2eabe
--- /dev/null
+++ b/src/mainboard/lenovo/w541/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/w541/acpi_tables.c b/src/mainboard/lenovo/w541/acpi_tables.c
new file mode 100644
index 0000000..04318b5
--- /dev/null
+++ b/src/mainboard/lenovo/w541/acpi_tables.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shut down. */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU. */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/lenovo/w541/board_info.txt b/src/mainboard/lenovo/w541/board_info.txt
new file mode 100644
index 0000000..02c0871
--- /dev/null
+++ b/src/mainboard/lenovo/w541/board_info.txt
@@ -0,0 +1,7 @@
+Category: laptop
+Board URL: https://www.lenovo.com/us/en/laptops/thinkpad/w-series/w541/
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2015
diff --git a/src/mainboard/lenovo/w541/cmos.default b/src/mainboard/lenovo/w541/cmos.default
new file mode 100644
index 0000000..facdd3a
--- /dev/null
+++ b/src/mainboard/lenovo/w541/cmos.default
@@ -0,0 +1,13 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+volume=0x3
+wlan=Enable
+fn_ctrl_swap=Disable
+f1_to_f12_as_primary=Enable
+sticky_fn=Disable
+trackpoint=Enable
+backlight=Keyboard
+enable_dual_graphics=Disable
+usb_always_on=Disable
diff --git a/src/mainboard/lenovo/w541/cmos.layout b/src/mainboard/lenovo/w541/cmos.layout
new file mode 100644
index 0000000..28790a7
--- /dev/null
+++ b/src/mainboard/lenovo/w541/cmos.layout
@@ -0,0 +1,76 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: EC
+415 1 e 1 wlan
+416 1 e 1 trackpoint
+417 1 e 1 fn_ctrl_swap
+418 1 e 1 sticky_fn
+419 2 e 13 usb_always_on
+422 2 e 10 backlight
+424 1 e 1 f1_to_f12_as_primary
+
+# coreboot config options: northbridge
+435 1 e 1 enable_dual_graphics
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# Haswell ThinkPads have no Thinklight
+#10 0 Both
+10 1 Keyboard
+#10 2 Thinklight only
+10 3 None
+13 0 Disable
+13 1 AC and battery
+13 2 AC only
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/lenovo/w541/data.vbt b/src/mainboard/lenovo/w541/data.vbt
new file mode 100644
index 0000000..519874f
--- /dev/null
+++ b/src/mainboard/lenovo/w541/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/w541/devicetree.cb b/src/mainboard/lenovo/w541/devicetree.cb
new file mode 100644
index 0000000..ae720e8
--- /dev/null
+++ b/src/mainboard/lenovo/w541/devicetree.cb
@@ -0,0 +1,99 @@
+chip northbridge/intel/haswell
+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+ register "gpu_ddi_e_connected" = "1"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 500,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 1,
+ .backlight_pwm_hz = 220,
+ }"
+ register "ec_present" = "true"
+ device cpu_cluster 0 on
+ chip cpu/intel/haswell
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0 on
+ subsystemid 0x17aa 0x2211 inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe graphics
+ device pci 02.0 on # iGPU
+ subsystemid 0x17aa 0x221e
+ end
+ device pci 03.0 on end # Mini-HD
+
+ chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+ register "gen1_dec" = "0x007c1601"
+ register "gen2_dec" = "0x000c15e1"
+ register "gen3_dec" = "0x00040291"
+ register "gen4_dec" = "0x000c06a1"
+ register "gpi13_routing" = "2"
+ register "gpi1_routing" = "2"
+ # 0(HDD), 1(I/O Subcard M.2), 4(WWAN/SSD M.2), 5(ODD)
+ register "sata_port_map" = "0x33"
+ device pci 14.0 on end # xHCI Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 on end # Management Engine KT
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x17aa 0x2210
+ end
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1f.0 on # LPC bridge
+ chip ec/lenovo/pmh7
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ device pnp ff.1 on end # dummy
+ end
+ chip ec/lenovo/h8 # FIXME: has_power_management_beeps, has_uwb
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+ register "config0" = "0xa6"
+ register "config1" = "0x05"
+ register "config2" = "0xa8"
+ register "config3" = "0xc4"
+ register "has_keyboard_backlight" = "1"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0x3c"
+ register "event7_enable" = "0x81"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventb_enable" = "0x08"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x9d"
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+ end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/w541/dsdt.asl b/src/mainboard/lenovo/w541/dsdt.asl
new file mode 100644
index 0000000..e3b5070
--- /dev/null
+++ b/src/mainboard/lenovo/w541/dsdt.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define EC_LENOVO_H8_ME_WORKAROUND 1
+#define THINKPAD_EC_GPE 17
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 // OEM revision
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ /* global NVS and variables. */
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/haswell/acpi/hostbridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/lenovo/w541/gma-mainboard.ads b/src/mainboard/lenovo/w541/gma-mainboard.ads
new file mode 100644
index 0000000..ad8a35b
--- /dev/null
+++ b/src/mainboard/lenovo/w541/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/w541/gpio.c b/src/mainboard/lenovo/w541/gpio.c
new file mode 100644
index 0000000..43baeb5
--- /dev/null
+++ b/src/mainboard/lenovo/w541/gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_OUTPUT,
+ .gpio4 = GPIO_DIR_OUTPUT,
+ .gpio5 = GPIO_DIR_OUTPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio3 = GPIO_LEVEL_LOW,
+ .gpio4 = GPIO_LEVEL_LOW,
+ .gpio5 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_HIGH,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_GPIO,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_GPIO,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_GPIO,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio65 = GPIO_DIR_INPUT,
+ .gpio66 = GPIO_DIR_INPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/lenovo/w541/hda_verb.c b/src/mainboard/lenovo/w541/hda_verb.c
new file mode 100644
index 0000000..a39510d
--- /dev/null
+++ b/src/mainboard/lenovo/w541/hda_verb.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0292, /* Codec Vendor / Device ID: Realtek ALC292*/
+ 0x17aa2211, /* Subsystem ID */
+ 32, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x17aa2211),
+ AZALIA_RESET(1),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x15, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40738105),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ 0x05350000, 0x0534601a, 0x05450000, 0x05442000,
+ 0x05350003, 0x05341ef8, 0x05450003, 0x05441ef8,
+ 0x05350016, 0x05341ee1, 0x05450016, 0x05441ee1,
+ 0x05350023, 0x05341f7b, 0x05450023, 0x05441f7b,
+ 0x05350030, 0x05341fbd, 0x05450030, 0x05441fbd,
+ 0x05350000, 0x0534e01a, 0x05450030, 0x05441fbd,
+ 0x02050020, 0x02048014, 0x02050020, 0x02040014,
+ 0x05350000, 0x0534e01a, 0x05450000, 0x0544e01a,
+ 0x0205001c, 0x02046800, 0x0205006d, 0x0204aa10,
+ 0x02050076, 0x02040009, 0x0205006b, 0x02045029,
+ 0x0205006c, 0x0204a400, 0x02050018, 0x02047208,
+ 0x0205001a, 0x02049ad2, 0x02050014, 0x02040710,
+ 0x02050079, 0x02040b40, 0x02050070, 0x02048800,
+ 0x00b3f410, 0x00c3f11f, 0x00c3f001, 0x015707c0,
+ 0x0153b080, 0x01470740, 0x0143b000, 0x02050004,
+ 0x02040080, 0x01470c02, 0x000f0000, 0x000f0000,
+ 0x02050029, 0x02040050, 0x02050025, 0x0204ebc2,
+ 0x02050026, 0x02044028, 0x02050029, 0x02040250,
+ 0x000f0000, 0x000f0000, 0x02050005, 0x0204ff1f,
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/w541/romstage.c b/src/mainboard/lenovo/w541/romstage.c
new file mode 100644
index 0000000..75b762a
--- /dev/null
+++ b/src/mainboard/lenovo/w541/romstage.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <option.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+#include <device/pci_ops.h>
+
+void mainboard_config_rcba(void)
+{
+ RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA);
+ RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC);
+ RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA);
+ RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD);
+ RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD);
+ RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH);
+ RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+ RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
+}
+
+void mb_late_romstage_setup(void)
+{
+ u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
+
+ bool power_en = pmh7_dgpu_power_state();
+
+ if (enable_peg != power_en)
+ pmh7_dgpu_power_enable(!power_en);
+
+ if (!enable_peg) {
+ // Hide disabled dGPU device
+ pci_and_config32(HOST_BRIDGE, DEVEN, ~DEVEN_D1F0EN);
+ }
+}
+
+void mb_get_spd_map(struct spd_info *spdi)
+{
+ spdi->addresses[0] = 0x50;
+ spdi->addresses[1] = 0x52;
+ spdi->addresses[2] = 0x51;
+ spdi->addresses[3] = 0x53;
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 0, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 1, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 2, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 3, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 4, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 5, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+ { 0x0040, 1, 6, USB_PORT_BACK_PANEL },
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ { 1, 0 },
+ { 1, 0 },
+ { 1, USB_OC_PIN_SKIP },
+ { 1, USB_OC_PIN_SKIP },
+ { 1, 1 },
+ { 1, 1 },
+};
diff --git a/src/mainboard/lenovo/w541/smihandler.c b/src/mainboard/lenovo/w541/smihandler.c
new file mode 100644
index 0000000..de48240
--- /dev/null
+++ b/src/mainboard/lenovo/w541/smihandler.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+#define GPE_EC_SCI 1
+#define GPE_EC_WAKE 13
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %#02x\n", event);
+}
+
+void mainboard_smi_gpi(u32 gpi_sts)
+{
+ if (gpi_sts & (1 << GPE_EC_SCI))
+ mainboard_smi_handle_ec_sci();
+}
+
+/* lynxpoint doesn't have gpi_route_interrupt, so add it */
+#define GPI_DISABLE 0x00
+#define GPI_IS_SMI 0x01
+#define GPI_IS_SCI 0x02
+#define GPI_IS_NMI 0x03
+
+static void gpi_route_interrupt(u8 gpi, u8 mode)
+{
+ u32 gpi_rout;
+
+ gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
+ gpi_rout &= ~(3 << (2 * gpi));
+ gpi_rout |= ((mode & 3) << (2 * gpi));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ switch (data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route EC_SCI to SCI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route EC_SCI to SMI */
+ gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (slp_typ == 3) {
+ u8 ec_wake = ec_read(0x32);
+ /* If EC wake events are enabled,
+ * enable wake on EC WAKE GPE. */
+ if (ec_wake & 0x14) {
+ /* Redirect EC WAKE GPE to SCI. */
+ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
+ }
+ }
+}