diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 76b3088..2cef5f2 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -74,8 +74,8 @@
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work
 	 */
-	sandybridge_early_initialization();
-	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+	systemagent_early_init();
+	printk(BIOS_DEBUG, "Back from systemagent_early_init()\n");
 
 	s3resume = southbridge_detect_s3_resume();