soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.
An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.
Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.
TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)
With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)
Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index c975b99..47709d9 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -204,11 +204,11 @@
register "gpio_override_pm" = "1"
# GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ register "gpio_pm[COMM_0]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ register "gpio_pm[COMM_2]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
+ register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
+ register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 6a807a3..f035b79 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -209,11 +209,11 @@
register "gpio_override_pm" = "1"
# GPIO community PM configuration
- register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ register "gpio_pm[COMM_0]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
- register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
- register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+ register "gpio_pm[COMM_2]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
+ register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
+ register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/google/volteer/mainboard.asl b/src/mainboard/google/volteer/mainboard.asl
index 0e9bb8c..5242845 100644
--- a/src/mainboard/google/volteer/mainboard.asl
+++ b/src/mainboard/google/volteer/mainboard.asl
@@ -16,7 +16,7 @@
*/
Method (MPTS, 1, Serialized)
{
- PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
}
/*
@@ -36,7 +36,7 @@
{
If (Arg0 == 1) {
/* S0ix Entry */
- PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
} Else {
/* S0ix Exit */
PGPM (0)
diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl
index e21f6d5..50d999f 100644
--- a/src/soc/intel/alderlake/acpi/gpio.asl
+++ b/src/soc/intel/alderlake/acpi/gpio.asl
@@ -166,6 +166,6 @@
/* Enable PM bits */
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
{
- CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS)
}
}
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index 9777052..dc54845 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -119,7 +119,7 @@
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h
index eec698a..acaade4 100644
--- a/src/soc/intel/alderlake/include/soc/gpio.h
+++ b/src/soc/intel/alderlake/include/soc/gpio.h
@@ -9,4 +9,10 @@
#define CROS_GPIO_NAME "INTC1055"
#define CROS_GPIO_DEVICE_NAME "INTC1055:00"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 9b809c0..f06b9f5 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -10,4 +10,11 @@
#endif
#include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in
soc/gpio_glk.h and soc/gpio_apl.h */
+
+/*
+ * APL/GLK doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl
index f1284e1..7776acc 100644
--- a/src/soc/intel/cannonlake/acpi/gpio.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio.asl
@@ -138,9 +138,9 @@
Store (GPID (Arg0), Local0)
If (LNotEqual (Local0, 0)) {
/* Mask off current PM bits */
- PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_ENABLE_GPIO_PM_CONFIG))
+ PCRA (Local0, GPIO_MISCCFG, Not (MISCCFG_GPIO_PM_CONFIG_BITS))
/* Mask in requested bits */
- PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_ENABLE_GPIO_PM_CONFIG))
+ PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_GPIO_PM_CONFIG_BITS))
}
}
@@ -181,6 +181,6 @@
/* Enable PM bits */
For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
{
- CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS)
}
}
diff --git a/src/soc/intel/cannonlake/gpio_common.c b/src/soc/intel/cannonlake/gpio_common.c
index 45331ec..21a5801 100644
--- a/src/soc/intel/cannonlake/gpio_common.c
+++ b/src/soc/intel/cannonlake/gpio_common.c
@@ -17,7 +17,7 @@
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h
index b39798e..9ffa8f1 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio.h
@@ -12,6 +12,11 @@
#endif
#include <intelblocks/gpio.h>
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#ifndef __ACPI__
struct pad_config;
void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads);
diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl
index dbfa7af..225f72a 100644
--- a/src/soc/intel/common/acpi/gpio.asl
+++ b/src/soc/intel/common/acpi/gpio.asl
@@ -11,8 +11,8 @@
Local0 = GPID (Arg0)
If (Local0 != 0) {
/* Mask off current PM bits */
- PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_GPIO_PM_CONFIG_BITS)
/* Mask in requested bits */
- PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG)
+ PCRO (Local0, GPIO_MISCCFG, Arg1 & MISCCFG_GPIO_PM_CONFIG_BITS)
}
}
diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl
index a973149..496f184 100644
--- a/src/soc/intel/common/acpi/platform.asl
+++ b/src/soc/intel/common/acpi/platform.asl
@@ -30,7 +30,7 @@
}
/*
* Save the current PM bits then
- * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
+ * enable GPIO PM with MISCCFG_GPIO_PM_CONFIG_BITS
*/
If (CondRefOf (\_SB.PCI0.EGPM))
{
diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl
index b6a0d9d..2e2a25f 100644
--- a/src/soc/intel/common/block/acpi/acpi/pep.asl
+++ b/src/soc/intel/common/block/acpi/acpi/pep.asl
@@ -91,7 +91,7 @@
/*
* Save the current PM bits then
- * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG
+ * enable GPIO PM with MISCCFG_GPIO_PM_CONFIG_BITS
*/
If (CondRefOf (\_SB.PCI0.EGPM))
{
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index c747f30..417dfb8 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -656,7 +656,7 @@
{
int i;
size_t gpio_communities;
- const uint8_t misccfg_pm_mask = (uint8_t)~MISCCFG_ENABLE_GPIO_PM_CONFIG;
+ const uint8_t misccfg_pm_mask = (uint8_t)~MISCCFG_GPIO_PM_CONFIG_BITS;
const struct pad_community *comm;
comm = soc_gpio_get_community(&gpio_communities);
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 45ae1da..3f79b19 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -6,6 +6,10 @@
#include <soc/gpio.h>
#include "gpio_defs.h"
+/* GPIO community IOSF sideband VNNREQ/ACK handshake */
+#define MISCCFG_GPVNNREQEN (1 << 7)
+/* GPIO community PGCB clock gating */
+#define MISCCFG_GPPGCBDPCGEN (1 << 6)
/* GPIO community IOSF sideband clock gating */
#define MISCCFG_GPSIDEDPCGEN (1 << 5)
/* GPIO community RCOMP clock gating */
@@ -18,10 +22,6 @@
#define MISCCFG_GPDPCGEN (1 << 1)
/* GPIO community local clock gating */
#define MISCCFG_GPDLCGEN (1 << 0)
-/* Enable GPIO community power management configuration */
-#define MISCCFG_ENABLE_GPIO_PM_CONFIG (MISCCFG_GPSIDEDPCGEN | \
- MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
- | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
#ifndef __ACPI__
#include <types.h>
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h
index fcf57ff..41438c2 100644
--- a/src/soc/intel/denverton_ns/include/soc/gpio.h
+++ b/src/soc/intel/denverton_ns/include/soc/gpio.h
@@ -33,4 +33,10 @@
#include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in
lines above and soc/gpio_defs.h */
+/*
+ * DNV doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif /* _SOC_DENVERTON_NS_GPIO_H_ */
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index f1c75b6..b14edd6 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -108,7 +108,7 @@
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/elkhartlake/include/soc/gpio.h b/src/soc/intel/elkhartlake/include/soc/gpio.h
index 367df82..47f792c 100644
--- a/src/soc/intel/elkhartlake/include/soc/gpio.h
+++ b/src/soc/intel/elkhartlake/include/soc/gpio.h
@@ -12,4 +12,10 @@
#define CROS_GPIO_COMM4_NAME "INT34C8:02"
#define CROS_GPIO_COMM5_NAME "INT34C8:03"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index 134d7cf..821a9e0 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -98,7 +98,7 @@
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/icelake/include/soc/gpio.h b/src/soc/intel/icelake/include/soc/gpio.h
index 3eae13f..5d4269d 100644
--- a/src/soc/intel/icelake/include/soc/gpio.h
+++ b/src/soc/intel/icelake/include/soc/gpio.h
@@ -8,4 +8,9 @@
#define CROS_GPIO_DEVICE_NAME "INT3455:00"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index c663d1f..1051fbc 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -114,7 +114,7 @@
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/jasperlake/include/soc/gpio.h b/src/soc/intel/jasperlake/include/soc/gpio.h
index 384c067..fa7f915 100644
--- a/src/soc/intel/jasperlake/include/soc/gpio.h
+++ b/src/soc/intel/jasperlake/include/soc/gpio.h
@@ -12,4 +12,10 @@
#define CROS_GPIO_COMM4_NAME "INT34C8:02"
#define CROS_GPIO_COMM5_NAME "INT34C8:03"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 283df83..b55dea8 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -8,4 +8,11 @@
soc/gpio_defs.h */
#define CROS_GPIO_DEVICE_NAME "INT344B:00"
+
+/*
+ * SPT PCH doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 024da15..2a0d7d0 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -119,7 +119,7 @@
memcpy(value, config->gpio_pm, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+ memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(uint8_t) *
TOTAL_GPIO_COMM);
gpio_pm_configure(value, TOTAL_GPIO_COMM);
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
index b9842b9..d8227df 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -8,4 +8,10 @@
#define CROS_GPIO_DEVICE_NAME "INT34C5:00"
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
#endif
diff --git a/src/soc/intel/xeon_sp/include/soc/gpio.h b/src/soc/intel/xeon_sp/include/soc/gpio.h
index 6e85d4e..04eb9ae 100644
--- a/src/soc/intel/xeon_sp/include/soc/gpio.h
+++ b/src/soc/intel/xeon_sp/include/soc/gpio.h
@@ -6,4 +6,10 @@
#include <soc/lewisburg_pch_gpio_defs.h>
#include <intelblocks/gpio.h>
+/*
+ * XEON SP series doesn't support dynamic GPIO PM hence GPIO community
+ * MISCCFG register doesn't have PM bits
+ */
+#define MISCCFG_GPIO_PM_CONFIG_BITS 0
+
#endif