| commit | 2ccbcc560f01a7cd646b5012c3f680623c43ef96 | [log] [tgz] |
|---|---|---|
| author | Tim Chu <Tim.Chu@quantatw.com> | Thu Dec 08 11:05:36 2022 +0000 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Tue Jan 24 12:48:18 2023 +0000 |
| tree | 0e160a153bb1cc1e6f88ddbaee891d47b9e68857 | |
| parent | 1364ac3478c69affce32840d92577f5a8da2eb8c [diff] [blame] |
soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SP Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. The chipset includes Emmitsburg PCH. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 72dee3e..c6333af 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -155,6 +155,7 @@ PCI_DID_INTEL_ADP_P_P2SB, PCI_DID_INTEL_ADP_S_P2SB, PCI_DID_INTEL_ADP_M_P2SB, + PCI_DID_INTEL_SPR_SP_P2SB, 0, };