soc/intel/cmn/block: Add smbus/p2sb device ids for SPR-SP
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched
on Jan. 10, 2023. The chipset includes Emmitsburg PCH.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 15a41ce..dbc1706 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4120,6 +4120,7 @@
#define PCI_DID_INTEL_GLK_SMBUS 0x31d4
#define PCI_DID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DID_INTEL_SPT_H_SMBUS 0xa123
+#define PCI_DID_INTEL_EBG_SMBUS 0x1bc9
#define PCI_DID_INTEL_LWB_SMBUS 0xa1a3
#define PCI_DID_INTEL_LWB_SMBUS_SUPER 0xa223
#define PCI_DID_INTEL_CNL_SMBUS 0x9da3
@@ -4192,6 +4193,7 @@
#define PCI_DID_INTEL_ADP_P_P2SB 0x7a20
#define PCI_DID_INTEL_ADP_S_P2SB 0x7aa0
#define PCI_DID_INTEL_ADP_M_P2SB 0x54a0
+#define PCI_DID_INTEL_SPR_SP_P2SB 0x1bc6
#define PCI_DID_INTEL_MTL_SOC_P2SB 0x7e20
#define PCI_DID_INTEL_MTL_IOE_M_P2SB 0x7eb8
#define PCI_DID_INTEL_MTL_IOE_P_P2SB 0x7ec8
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 72dee3e..c6333af 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -155,6 +155,7 @@
PCI_DID_INTEL_ADP_P_P2SB,
PCI_DID_INTEL_ADP_S_P2SB,
PCI_DID_INTEL_ADP_M_P2SB,
+ PCI_DID_INTEL_SPR_SP_P2SB,
0,
};
diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index 6d6e8c8..d482e26 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -56,6 +56,7 @@
PCI_DID_INTEL_GLK_SMBUS,
PCI_DID_INTEL_CNL_SMBUS,
PCI_DID_INTEL_CNP_H_SMBUS,
+ PCI_DID_INTEL_EBG_SMBUS,
PCI_DID_INTEL_LWB_SMBUS_SUPER,
PCI_DID_INTEL_LWB_SMBUS,
PCI_DID_INTEL_ICP_LP_SMBUS,