tree 304d4206cb923aba3e058bc32bf30e75e8676876
parent 83e6c15b0ea252d5475c3a5af25279765e19aa4d
author John Zhao <john.zhao@intel.com> 1613496167 -0800
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1614118444 +0000

soc/intel/tigerlake: Remove polling for Link Active Status at resume

Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not
applicable for SW CM platform at the resume sequence. This change
removes the pollng for "LA == 1" to improve resume performance.

BUG=b:177519081
TEST=Boot to kernel and validated s0ix on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>