intel: Do not hardcode the position of mrc.cache
The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.
Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.
Signed-off-by: Alexandru Gagniuc <email@example.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <firstname.lastname@example.org>
Reviewed-by: Aaron Durbin <email@example.com>
9 files changed