nb/intel/sandybridge/acpi: Don't use defines for memory ranges
Read the northbridge BARs from device PCI0:0.0.
Untested.
Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 09b8892..4c4a509 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -31,24 +31,24 @@
Offset (0x40), // EPBAR
EPEN, 1, // Enable
, 11, //
- EPBR, 24, // EPBAR
+ EPBR, 27, // EPBAR
Offset (0x48), // MCHBAR
MHEN, 1, // Enable
- , 13, //
- MHBR, 22, // MCHBAR
+ , 14, //
+ MHBR, 24, // MCHBAR
Offset (0x54),
DVEN, 32,
Offset (0x60), // PCIe BAR
PXEN, 1, // Enable
PXSZ, 2, // BAR size
, 23, //
- PXBR, 10, // PCIe BAR
+ PXBR, 13, // PCIe BAR
Offset (0x68), // DMIBAR
DMEN, 1, // Enable
, 11, //
- DMBR, 24, // DMIBAR
+ DMBR, 27, // DMIBAR
Offset (0x70), // ME Base Address
MEBA, 64,
@@ -103,7 +103,7 @@
Name (CTCD, 1) /* CTDP Down Select */
Name (CTCU, 2) /* CTDP Up Select */
- OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
+ OperationRegion (MCHB, SystemMemory, \_SB.PCI0.MCHC.MHBR << 15, 0x8000)
Field (MCHB, DWordAcc, Lock, Preserve)
{
Offset (0x5930),
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index dce9f67..7fdfe42 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/
-#include "../sandybridge.h"
#include "hostbridge.asl"
#include "peg.asl"
@@ -27,12 +26,13 @@
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
- Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
- Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
- Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
+ // Filled by _CRS
+ Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB)
+ Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB)
+ Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB)
+ Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
- Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
#if CONFIG(CHROMEOS_RAMOOPS)
@@ -48,6 +48,21 @@
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
+ CreateDwordField (PDRS, ^MCHB._BAS, MBR0)
+ MBR0 = \_SB.PCI0.MCHC.MHBR << 15
+
+ CreateDwordField (PDRS, ^DMIB._BAS, DBR0)
+ DBR0 = \_SB.PCI0.MCHC.DMBR << 12
+
+ CreateDwordField (PDRS, ^EGPB._BAS, EBR0)
+ EBR0 = \_SB.PCI0.MCHC.EPBR << 12
+
+ CreateDwordField (PDRS, ^PCIX._BAS, XBR0)
+ XBR0 = \_SB.PCI0.MCHC.PXBR << 26
+
+ CreateDwordField (PDRS, ^PCIX._LEN, XSZ0)
+ XSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ
+
Return(PDRS)
}
}