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review.coreboot.org / coreboot / 2ac743330c2668abae9eb1d5a01ad1b86ba918a9
commit2ac743330c2668abae9eb1d5a01ad1b86ba918a9[log] [tgz]
authorPaul Menzel <pmenzel@molgen.mpg.de>Sat Mar 07 11:15:03 2020 +0100
committerAngel Pons <th3fanbus@gmail.com>Wed Oct 21 12:29:44 2020 +0000
treef6100eae21855931e8602528b8be6082563e3cbc
parent8fed9d638dcb7ce89880714eb58373205722f749 [diff]
mb/asus/f2a85-m_pro: Enable UART A in Super I/O

Currently, the serial console does not work.

With the serial port enabled in the vendor firmware, `superiotool` outputs
the global control register values below.

    Found Nuvoton NCT6779D (id=0xc562) at 0x2e
    Register dump:
    idx 10 11 13 14 1a 1b 1c 1d  20 21 22 24 25 26 27 28  2a 2b 2c 2f
    val ff ff ff ff 3a 28 00 10  c5 62 df 04 00 00 10 00  48 20 00 01
    def ff ff 00 00 30 70 10 00  c5 62 ff 04 00 MM 00 00  c0 00 01 MM

UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by
selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`.
This changes the default value 0xc0 to 0x40.

Note, due configuring the system as legacy free with
`HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in
`FchInitResetLpcProgram()`.

    coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)...
    APIC 00: CPU Family_Model = 00610f31

    APIC 00: ** Enter AmdInitReset [00020007]
    Fch OEM config in INIT RESET

`AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only
when coreboot enables the LPC controller again in ramstage, serial output
continues.

    PCI: 00:14.4 bridge ctrl <- 0013
    PCI: 00:14.4 cmd <- 00
    PCI: 00:14.5 cmd <- 02
    PCI: 00:15.0 bridge ctrl <- 0013
    PCI: 00:15.0 cmd <- 00
    PCI: 00:15.1 bridge ctrl <- 0013
    […]
    done.
    BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms
    Initializing devices...
    CPU_CLUSTER: 0 init
    […]

Note, due to incorrect Super I/O configuration in the devicetree, the boot
hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This
will be fixed in follow-up commits.

TEST=Receive (some) coreboot log messages over the serial console.
Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1 file changed
tree: f6100eae21855931e8602528b8be6082563e3cbc
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.