tree 7e3290a0badc28cb7d5f3aa8368ec8769b75d8a9
parent c3c3e453ff4e6d73b52d88ab08a708610997f334
author Bora Guvendik <bora.guvendik@intel.com> 1605554628 -0800
committer Patrick Georgi <pgeorgi@google.com> 1606084484 +0000

soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars

BAR address used during early initilization of GPSI 2 is overlapping with UART bar.

//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)

//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000

TEST=none

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>