mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 479a7ee..51a39c0 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -3,6 +3,104 @@
device lapic 0 on end
end
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+
+ # Enable WLAN PCIE 5 using clk 2
+ register "PchPcieRpEnable[5]" = "1"
+ register "PcieRpLtrEnable[5]" = "1"
+ register "PcieClkSrcUsage[2]" = "5"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+
+ # Enable WWAN PCIE 6 using clk 5
+ register "PchPcieRpEnable[6]" = "1"
+ register "PcieRpLtrEnable[6]" = "1"
+ register "PcieClkSrcUsage[5]" = "6"
+ register "PcieClkSrcClkReq[5]" = "5"
+ register "PcieRpAdvancedErrorReporting[6]" = "1"
+
+ # Enable SD Card PCIE 8 using clk 3
+ register "PchPcieRpEnable[7]" = "1"
+ register "PcieRpLtrEnable[7]" = "1"
+ register "PcieRpHotPlug[7]" = "1"
+ register "PcieClkSrcUsage[3]" = "7"
+ register "PcieClkSrcClkReq[3]" = "3"
+ register "PcieRpAdvancedErrorReporting[7]" = "1"
+
+ # Enable NVMe PCIE 9 using clk 1
+ register "PchPcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieClkSrcUsage[1]" = "8"
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | SAR0 |
+ #| I2C3 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C4 | CAM |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
device domain 0 on
device ref igpu on end
device ref dtt on end
@@ -23,14 +121,11 @@
end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp1 on end #USB3-1 Type A
- device ref pcie_rp4 on end #USB3-4 WWAN
device ref pcie_rp5 on end #PCIE5 WLAN
device ref pcie_rp6 on end #PCIE6 WWAN
device ref pcie_rp8 on end #PCIE8 SD card
device ref pcie_rp9 on end #PCIE9-12 SSD
device ref uart0 on end
- device ref gspi0 on end
device ref gspi1 on end
device ref pch_espi on
chip ec/google/chromeec