tree 4d649d3090c4a1acafb970049c2c901d2396e71e
parent ffd75c29365f1493dc0ef9abdd797653dfb56be6
author Nico Huber <nico.h@gmx.de> 1652536651 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1656088113 +0000

nb/intel/gm45/acpi: Fix max PCI bus number

Commit 0cc56a2848 (nb/intel/gm45/dsdt: Fix number of PCI busses) derives
the maximum PCI bus number at runtime. However, IASL complains about the
initial 0 in the resource template, which rendered the PB00 definition
self-contradictory at build time (maximum was lower than minimum +
length - 1).

Let's return to the old default values (min: 0, max: 255, length: 256)
and adapt max and length at runtime. Also fix some surrounding whites-
pace.

NB. The issue wasn't detected before merging commit 0cc56a2848 because
of broken IASL versions that can't count errors.

Change-Id: I359d357f276feda8fe04383080d51dc492c3f2e8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64347
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Ott <coreboot@desire.ch>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>