diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 6ff82dd..7d684b2 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -176,10 +176,12 @@
 
 	/* 100 MHz reference clock supported */
 	reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B);
-	ref_100mhz_support = !!((reg32 >> 21) & 0x7);
+	ref_100mhz_support = (reg32 >> 21) & 0x7;
 	printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes"
 										      : "no");
 
+	printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support);
+
 	/* Find CAS latency */
 	while (1) {
 		/*