Port Fam14 northbridge code to 64bit
Change-Id: I694b739a29e9d82d153d9fb3b729dc250bd4901e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10583
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index fcc0d87..7a0294b 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -529,7 +529,7 @@
static void domain_set_resources(device_t dev)
{
printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
- printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
+ printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev);
unsigned long mmio_basek;
u32 pci_tolm;
@@ -741,11 +741,13 @@
addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
if (addr != NULL)
- current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+ current += acpi_create_hest_error_source(hest, current, 0,
+ addr + 2, *(UINT16 *)addr - 2);
addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
if (addr != NULL)
- current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+ current += acpi_create_hest_error_source(hest, current, 1,
+ addr + 2, *(UINT16 *)addr - 2);
return (unsigned long)current;
}
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index 77bab67..5f02815 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -39,7 +39,7 @@
#error "Please increase the value of S3_DATA_SIZE"
#endif
-static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len)
+static void get_s3nv_data(S3_DATA_TYPE S3DataType, uintptr_t *pos, uintptr_t *len)
{
/* FIXME: Find file from CBFS. */
u32 s3_data = CONFIG_S3_DATA_POS;
@@ -65,7 +65,7 @@
AGESA_STATUS OemInitResume(AMD_RESUME_PARAMS *ResumeParams)
{
AMD_S3_PARAMS *dataBlock = &ResumeParams->S3DataBlock;
- u32 pos, size;
+ uintptr_t pos, size;
get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
@@ -126,7 +126,7 @@
#endif
u8 MTRRStorage[S3_DATA_MTRR_SIZE];
u32 MTRRStorageSize = 0;
- u32 pos, size;
+ uintptr_t pos, size;
if (HIGH_ROMSTAGE_STACK_SIZE)
cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
@@ -157,7 +157,7 @@
const void *OemS3Saved_MTRR_Storage(void)
{
- u32 pos, size;
+ uintptr_t pos, size;
get_s3nv_data(S3DataTypeMTRR, &pos, &size);
if (!size)
return NULL;