soc/intel/common/uart: Drop chip in favor of devicetree ops
It is now possible to hook up device ops directly to devices in
devicetree which removes the need for a fake chip.
This also fixes Hermes booting as the PCI ops were incorrectly hooked up
to a dummy device. The intel uart driver was requesting a resource from
the generic device and died since it does not exist:
[EMERG] GENERIC: 0.0 missing resource: 10
This was broken in commit b9165199c32a (mb/prodrive/hermes: Rework UART
devicetree entry).
Change-Id: I3b32d1cc52afaed2a321eea5815f2957fe730f79
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82940
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb
index ea9f673..ee73800 100644
--- a/src/mainboard/prodrive/hermes/devicetree.cb
+++ b/src/mainboard/prodrive/hermes/devicetree.cb
@@ -170,12 +170,7 @@
# This device does not have any function on CNP-H, but it needs
# to be here so that the resource allocator is aware of UART 2.
device ref i2c4 hidden end
- device ref uart2 hidden # in ACPI mode
- chip soc/intel/common/block/uart
- register "devid" = "PCI_DID_INTEL_CNP_H_UART2"
- device generic 0 hidden end
- end
- end
+ device ref uart2 hidden end # in ACPI mode
device ref pcie_rp21 on
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
register "PcieRpEnable[20]" = "1"
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index bda66bd..e2e4a6b 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -2,6 +2,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ids.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <gpio.h>
@@ -153,10 +154,20 @@
soc_gpio_pm_configuration();
/* swap enabled PCI ports in device tree if needed */
- if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
+ if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) {
pcie_rp_update_devicetree(pch_h_rp_groups);
- else
+
+ /*
+ * Fix up device ID of hidden PCI device in devicetree.
+ * This is used by soc/intel/common/block/uart.c to generate ACPI
+ */
+ struct device *uart2 = PCH_DEV_UART2;
+ if (uart2->hidden)
+ uart2->device = PCI_DID_INTEL_CNP_H_UART2;
+
+ } else {
pcie_rp_update_devicetree(pch_lp_rp_groups);
+ }
}
static void cpu_fill_ssdt(const struct device *dev)
diff --git a/src/soc/intel/cannonlake/chipset_pch_h.cb b/src/soc/intel/cannonlake/chipset_pch_h.cb
index 022e31f..77c0d84 100644
--- a/src/soc/intel/cannonlake/chipset_pch_h.cb
+++ b/src/soc/intel/cannonlake/chipset_pch_h.cb
@@ -92,7 +92,9 @@
device pci 17.0 alias sata off end # SATA
device pci 19.0 alias i2c4 off end # I2C #4
device pci 19.1 alias i2c5 off end # I2C #5
- device pci 19.2 alias uart2 off end # UART #2
+ device pci 19.2 alias uart2 off # UART #2
+ ops uart_ops
+ end
device pci 1a.0 alias emmc off end # eMMC
device pci 1b.0 alias pcie_rp17 off end # PCI Express Port 17
device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18
diff --git a/src/soc/intel/common/block/uart/chip.h b/src/soc/intel/common/block/uart/chip.h
deleted file mode 100644
index 5981126..0000000
--- a/src/soc/intel/common/block/uart/chip.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <stdint.h>
-/* Indirect include for static.c: */
-#include <device/pci_ids.h>
-
-#ifndef _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_
-#define _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_
-
-struct soc_intel_common_block_uart_config {
- /* The Device ID read from config space at offset[2:4] when not hidden */
- u16 devid;
-};
-
-#endif /* _SOC_INTEL_COMMON_BLOCK_UART_CHIP_H_ */
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index e52bb0f..e454f7e 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -14,7 +14,6 @@
#include <soc/pci_devs.h>
#include <soc/iomap.h>
#include <soc/nvs.h>
-#include "chip.h"
#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
@@ -430,17 +429,4 @@
.vendor = PCI_VID_INTEL,
.devices = pci_device_ids,
};
-
-static void uart_enable(struct device *dev)
-{
- struct soc_intel_common_block_uart_config *conf = dev->chip_info;
- dev->ops = &uart_ops;
- dev->device = conf ? conf->devid : 0;
-}
-
-struct chip_operations soc_intel_common_block_uart_ops = {
- .name = "LPSS UART in ACPI mode",
- .enable_dev = uart_enable
-};
-
#endif /* ENV_RAMSTAGE */