soc/intel/broadwell: Rename `SA_DEV_ROOT`
For consistency with Haswell, rename this macro to `HOST_BRIDGE`.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I4319f04c67aec8df118fa539e00c7328128f0700
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55528
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c
index 9de757e..bd88195 100644
--- a/src/soc/intel/broadwell/bootblock.c
+++ b/src/soc/intel/broadwell/bootblock.c
@@ -29,6 +29,6 @@
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, 0);
- pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
+ pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
+ pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}
diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c
index 9b523d8..284e877 100644
--- a/src/soc/intel/broadwell/early_init.c
+++ b/src/soc/intel/broadwell/early_init.c
@@ -11,32 +11,32 @@
static void broadwell_setup_bars(void)
{
/* Set up all hardcoded northbridge BARs */
- pci_write_config32(SA_DEV_ROOT, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
- pci_write_config32(SA_DEV_ROOT, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
- pci_write_config32(SA_DEV_ROOT, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
+ pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
+ pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
+ pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1);
mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1);
/* Set C0000-FFFFF to access RAM on both reads and writes */
- pci_write_config8(SA_DEV_ROOT, PAM0, 0x30);
- pci_write_config8(SA_DEV_ROOT, PAM1, 0x33);
- pci_write_config8(SA_DEV_ROOT, PAM2, 0x33);
- pci_write_config8(SA_DEV_ROOT, PAM3, 0x33);
- pci_write_config8(SA_DEV_ROOT, PAM4, 0x33);
- pci_write_config8(SA_DEV_ROOT, PAM5, 0x33);
- pci_write_config8(SA_DEV_ROOT, PAM6, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
+ pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
+ pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
}
void systemagent_early_init(void)
{
const bool vtd_capable =
- !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE);
+ !(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE);
broadwell_setup_bars();
/* Device enable: IGD and Mini-HD */
- pci_write_config32(SA_DEV_ROOT, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
+ pci_write_config32(HOST_BRIDGE, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
if (vtd_capable) {
/* setup BARs: zeroize top 32 bits; set enable bit */
diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h
index 3cf7cf3..b49023c 100644
--- a/src/soc/intel/broadwell/include/soc/pci_devs.h
+++ b/src/soc/intel/broadwell/include/soc/pci_devs.h
@@ -17,9 +17,7 @@
#define SA_DEV_SLOT_ROOT 0x00
#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)
-#if defined(__SIMPLE_DEVICE__)
-#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
-#endif
+#define HOST_BRIDGE PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
#define SA_DEV_SLOT_IGD 0x02
#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index f7e58af..b467dc0 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -19,7 +19,7 @@
* 1 MiB alignment and reports the TOP of the range, the base
* must be calculated from the size in MiB in bits 11:4.
*/
- uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
+ uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR);
uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB);
/* Subtract DMA Protected Range size if enabled */
@@ -36,8 +36,8 @@
void smm_region(uintptr_t *start, size_t *size)
{
- uintptr_t tseg = pci_read_config32(SA_DEV_ROOT, TSEG);
- uintptr_t bgsm = pci_read_config32(SA_DEV_ROOT, BGSM);
+ uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG);
+ uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM);
tseg = ALIGN_DOWN(tseg, 1 * MiB);
bgsm = ALIGN_DOWN(bgsm, 1 * MiB);
diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c
index 018ea24..7e044be 100644
--- a/src/soc/intel/broadwell/report_platform.c
+++ b/src/soc/intel/broadwell/report_platform.c
@@ -124,8 +124,8 @@
static void report_mch_info(void)
{
int i;
- u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
- u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
+ u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID);
+ u8 mch_revision = pci_read_config8(HOST_BRIDGE, PCI_REVISION_ID);
const char *mch_type = "Unknown";
/* Look for string to match the revision for Broadwell U/Y */