diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 6e492bb..77bad8f 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -50,7 +50,11 @@
 	m_cfg->PcieRpEnableMask = mask;
 	m_cfg->PrmrrSize = config->PrmrrSize;
 	m_cfg->EnableC6Dram = config->enable_c6dram;
+#if CONFIG(SOC_INTEL_COMETLAKE)
+	m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+#else
 	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
+#endif
 	/*
 	 * PcdDebugInterfaceFlags
 	 * This config will allow coreboot to pass information to the FSP