diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index b873a03..33acf43 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -8,15 +8,22 @@
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_BOOTBLOCK_X86_32
+	select ARCH_ROMSTAGE_X86_32
+	select ARCH_VERSTAGE_X86_32
 	select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
 	select BOOT_DEVICE_SUPPORTS_WRITES
+	select CACHE_MRC_SETTINGS
+	select CPU_INTEL_COMMON
+	select FSP_M_XIP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select IDT_IN_EVERY_STAGE
 	select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
+	select MRC_SETTINGS_PROTECT
 	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_2
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_BLOCK
+	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
 	select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
 	select SOC_INTEL_COMMON_BLOCK_SA
@@ -120,6 +127,13 @@
 config CHROMEOS
 	select CHROMEOS_RAMOOPS_DYNAMIC
 
+config VBOOT
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_MUST_REQUEST_DISPLAY
+	select VBOOT_STARTS_IN_BOOTBLOCK
+	select VBOOT_VBNV_CMOS
+	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+
 config C_ENV_BOOTBLOCK_SIZE
 	hex
 	default 0xC000
@@ -139,4 +153,20 @@
 	string
 	depends on FSP_USE_REPO
 	default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
+
+config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
+	int "Debug Consent for ADL"
+	# USB DBC is more common for developers so make this default to 3 if
+	# SOC_INTEL_DEBUG_CONSENT=y
+	default 3 if SOC_INTEL_DEBUG_CONSENT
+	default 0
+	help
+	  This is to control debug interface on SOC.
+	  Setting non-zero value will allow to use DBC or DCI to debug SOC.
+	  PlatformDebugConsent in FspmUpd.h has the details.
+
+	  Desired platform debug type are
+	  0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
+	  3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
+	  6:Enable (2-wire DCI OOB), 7:Manual
 endif