vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSP
This file started as a copy from Cezanne. Sabrina has less USB ports
than Cezanne. Also the struct definition of fch_usb2_phy has changed and
FSP_USB_STRUCT_MINOR_VERSION is also updated.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/vendorcode/amd/fsp/sabrina/FspUsb.h b/src/vendorcode/amd/fsp/sabrina/FspUsb.h
index fea1fee..19fac35 100644
--- a/src/vendorcode/amd/fsp/sabrina/FspUsb.h
+++ b/src/vendorcode/amd/fsp/sabrina/FspUsb.h
@@ -4,29 +4,32 @@
#include <FspUpd.h>
#define FSP_USB_STRUCT_MAJOR_VERSION 0xd
-#define FSP_USB_STRUCT_MINOR_VERSION 0x6
+#define FSP_USB_STRUCT_MINOR_VERSION 0xe
-#define USB2_PORT_COUNT 8
-#define USB3_PORT_COUNT 4
+#define USB2_PORT_COUNT 6
+#define USB3_PORT_COUNT 3
#define USBC_COMBO_PHY_COUNT 2
struct fch_usb2_phy {
- uint8_t compdstune; ///< COMPDSTUNE
- uint8_t sqrxtune; ///< SQRXTUNE
- uint8_t txfslstune; ///< TXFSLSTUNE
- uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE
- uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE
- uint8_t txrisetune; ///< TXRISETUNE
- uint8_t txvreftune; ///< TXVREFTUNE
- uint8_t txhsxvtune; ///< TXHSXVTUNE
- uint8_t txrestune; ///< TXRESTUNE
+ uint8_t compdistune; ///< COMPDISTUNE
+ uint8_t pllbtune; ///< PLLBTUNE
+ uint8_t pllitune; ///< PLLITUNE
+ uint8_t pllptune; ///< PLLPTUNE
+ uint8_t sqrxtune; ///< SQRXTUNE
+ uint8_t txfslstune; ///< TXFSLSTUNE
+ uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE
+ uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE
+ uint8_t txrisetune; ///< TXRISETUNE
+ uint8_t txvreftune; ///< TXVREFTUNE
+ uint8_t txhsxvtune; ///< TXHSXVTUNE
+ uint8_t txrestune; ///< TXRESTUNE
} __packed;
struct fch_usb3_phy {
- uint8_t tx_term_ctrl; ///< tx_term_ctrl
- uint8_t rx_term_ctrl; ///< rx_term_ctrl
- uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN
- uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL
+ uint8_t tx_term_ctrl; ///< tx_term_ctrl
+ uint8_t rx_term_ctrl; ///< rx_term_ctrl
+ uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN
+ uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL
} __packed;
#define USB0_PORT0 0