| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| #ifndef AMD_BLOCK_DATA_FABRIC_DEF_H |
| #define AMD_BLOCK_DATA_FABRIC_DEF_H |
| |
| #define DF_FICAA_BIOS 0x5C |
| #define DF_FICAD_LO 0x98 |
| #define DF_FICAD_HI 0x9C |
| |
| #define DF_IND_CFG_INST_ACC_EN (1 << 0) |
| #define DF_IND_CFG_ACC_REG_SHIFT 2 |
| #define DF_IND_CFG_ACC_REG_MASK (0x1ff << DF_IND_CFG_ACC_REG_SHIFT) |
| #define DF_IND_CFG_ACC_FUN_SHIFT 11 |
| #define DF_IND_CFG_ACC_FUN_MASK (0x7 << DF_IND_CFG_ACC_FUN_SHIFT) |
| #define DF_IND_CFG_64B_EN_SHIFT 14 |
| #define DF_IND_CFG_64B_EN (0x1 << DF_IND_CFG_64B_EN_SHIFT) |
| #define DF_IND_CFG_INST_ID_SHIFT 16 |
| #define DF_IND_CFG_INST_ID_MASK (0xff << DF_IND_CFG_INST_ID_SHIFT) |
| |
| #endif /* AMD_BLOCK_DATA_FABRIC_DEF_H */ |