nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
existing bootblock_mainboard_early_init().
Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 3adf698..ba9616d 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -21,6 +21,7 @@
select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS
select HAVE_DEBUG_RAM_SETUP
+ select C_ENVIRONMENT_BOOTBLOCK
if NORTHBRIDGE_INTEL_NEHALEM
@@ -48,9 +49,12 @@
hex
default 0x10000
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/intel/nehalem/bootblock.c"
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2000
+ help
+ The amount of anticipated stack usage in CAR by bootblock and
+ other stages.
config MRC_CACHE_SIZE
hex
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index 3b12bb5..225f0ce 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
+bootblock-y += bootblock.c
+
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += smi.c
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c
index f96ff56..46cdef0 100644
--- a/src/northbridge/intel/nehalem/bootblock.c
+++ b/src/northbridge/intel/nehalem/bootblock.c
@@ -12,8 +12,9 @@
*/
#include <device/pci_ops.h>
+#include <cpu/intel/car/bootblock.h>
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
{
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1);
pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0);
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c
index 54766de..8188303 100644
--- a/src/northbridge/intel/nehalem/romstage.c
+++ b/src/northbridge/intel/nehalem/romstage.c
@@ -45,11 +45,6 @@
/* TODO, make this configurable */
nehalem_early_initialization(NEHALEM_MOBILE);
- pch_pre_console_init();
-
- /* Initialize console device(s) */
- console_init();
-
early_pch_init();
/* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */