tree d4dfdc04eb5ed56fe0a9c2ce87dc738fbbfafdf7
parent 95bab4077ee564835a8e2f2f8675c567d5283a86
author Subrata Banik <subrata.banik@intel.com> 1601186458 +0530
committer Subrata Banik <subrata.banik@intel.com> 1601727322 +0000

soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API

Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>