soc/intel/common/thermal: Refactor thermal block to improve reusability
This patch moves common thermal API between chipsets
with thermal device as PCI device and thermal device behind PMC
into common file (thermal_common.c).
Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC
Kconfig to select as applicable for underlying chipset.
+------------------------------------------------------+--------------+
| Thermal Kconfig | SoC |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL |
| | till ICL |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards |
| | ICL |
+------------------------------------------------------+--------------+
Either of these two Kconfig internally selects
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.
Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/common/block/thermal/thermal_pci.c b/src/soc/intel/common/block/thermal/thermal_pci.c
new file mode 100644
index 0000000..1b9f28a
--- /dev/null
+++ b/src/soc/intel/common/block/thermal/thermal_pci.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <intelblocks/thermal.h>
+#include <soc/pci_devs.h>
+
+#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c
+#define CATASTROPHIC_TRIP_POINT_MASK 0x1ff
+
+/* Enable thermal sensor power management */
+void pch_thermal_configuration(void)
+{
+ uintptr_t thermalbar;
+ uintptr_t thermalbar_pm;
+ const struct device *dev;
+ struct resource *res;
+
+ dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
+ if (!dev) {
+ printk(BIOS_ERR, "ERROR: PCH_DEVFN_THERMAL device not found!\n");
+ return;
+ }
+
+ res = probe_resource(dev, PCI_BASE_ADDRESS_0);
+ if (!res) {
+ printk(BIOS_ERR, "ERROR: PCH thermal device not found!\n");
+ return;
+ }
+
+ /* Get the base address of the resource */
+ thermalbar = res->base;
+
+ /* Get the required thermal address to write the register value */
+ thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT;
+
+ /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */
+ clrsetbits32((void *)thermalbar_pm, CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value());
+}