diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 4ab58d4..1507d6f2 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -212,16 +212,17 @@
 	default 10 if SOC_INTEL_ALDERLAKE_PCH_M
 	default 12 if SOC_INTEL_ALDERLAKE_PCH_N
 	default 12 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 28 if SOC_INTEL_ALDERLAKE_PCH_S
 
 config MAX_CPU_ROOT_PORTS
 	int
 	default 1 if SOC_INTEL_ALDERLAKE_PCH_M
 	default 0 if SOC_INTEL_ALDERLAKE_PCH_N
-	default 3 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S
 
 config MAX_TBT_ROOT_PORTS
 	int
-	default 0 if SOC_INTEL_ALDERLAKE_PCH_N
+	default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S
 	default 2 if SOC_INTEL_ALDERLAKE_PCH_M
 	default 4 if SOC_INTEL_ALDERLAKE_PCH_P
 
@@ -234,12 +235,14 @@
 	default 6 if SOC_INTEL_ALDERLAKE_PCH_M
 	default 5 if SOC_INTEL_ALDERLAKE_PCH_N
 	default 7 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 18 if SOC_INTEL_ALDERLAKE_PCH_S
 
 config MAX_PCIE_CLOCK_REQ
 	int
 	default 6  if SOC_INTEL_ALDERLAKE_PCH_M
 	default 5  if SOC_INTEL_ALDERLAKE_PCH_N
 	default 10 if SOC_INTEL_ALDERLAKE_PCH_P
+	default 18 if SOC_INTEL_ALDERLAKE_PCH_S
 
 config SMM_TSEG_SIZE
 	hex