| commit | 2765a893ca355caaf7d859e2bff5eb58630e2ddb | [log] [tgz] |
|---|---|---|
| author | Elyes HAOUAS <ehaouas@noos.fr> | Thu Sep 01 19:44:56 2016 +0200 |
| committer | Martin Roth <martinroth@google.com> | Sun Sep 04 05:33:04 2016 +0200 |
| tree | 80ca397f44651f9bda94ff891746f89b23013ee6 | |
| parent | d1cab6650261a2e6e75ff85b1868d723f1e1cc79 [diff] [blame] |
src/cpu: Improve code formatting Change-Id: I17d5efe382da5301a9f5d595186d0fb7576725ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16391 Tested-by: build bot (Jenkins) Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Antonello Dettori <dev@dettori.io>
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 3e2b3e2..024133b 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -200,7 +200,7 @@ post_code(0x27) /* Do not disable cache (so BSP can enable it). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0