diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index f70cc6e..b967583 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -805,49 +805,46 @@
 {
 	int ch, lane;
 
-	FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		for (lane = 0; lane < 8; lane++) {
-			switch (s->selected_timings.mem_clk) {
-			case MEM_CLOCK_667MHz:
+	FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) {
+		switch (s->selected_timings.mem_clk) {
+		case MEM_CLOCK_667MHz:
+			memcpy(s->dqs_settings[ch],
+				default_ddr2_667_dqs,
+				sizeof(s->dqs_settings[ch]));
+			memcpy(s->dq_settings[ch],
+				default_ddr2_667_dq,
+				sizeof(s->dq_settings[ch]));
+			s->rt_dqs[ch][lane].tap = 7;
+			s->rt_dqs[ch][lane].pi = 2;
+			break;
+		case MEM_CLOCK_800MHz:
+			if (s->spd_type == DDR2) {
 				memcpy(s->dqs_settings[ch],
-					default_ddr2_667_dqs,
+					default_ddr2_800_dqs,
 					sizeof(s->dqs_settings[ch]));
 				memcpy(s->dq_settings[ch],
-					default_ddr2_667_dq,
+					default_ddr2_800_dq,
 					sizeof(s->dq_settings[ch]));
 				s->rt_dqs[ch][lane].tap = 7;
-				s->rt_dqs[ch][lane].pi = 2;
-				break;
-			case MEM_CLOCK_800MHz:
-				if (s->spd_type == DDR2) {
-					memcpy(s->dqs_settings[ch],
-						default_ddr2_800_dqs,
-						sizeof(s->dqs_settings[ch]));
-					memcpy(s->dq_settings[ch],
-						default_ddr2_800_dq,
-						sizeof(s->dq_settings[ch]));
-
-					s->rt_dqs[ch][lane].tap = 7;
-					s->rt_dqs[ch][lane].pi = 0;
-				} else { /* DDR3 */
-					/* TODO: DDR3 write DQ-DQS */
-					s->rt_dqs[ch][lane].tap = 6;
-					s->rt_dqs[ch][lane].pi = 2;
-				}
-				break;
-			case MEM_CLOCK_1066MHz:
-				/* TODO: DDR3 write DQ-DQS */
-				s->rt_dqs[ch][lane].tap = 5;
-				s->rt_dqs[ch][lane].pi = 2;
-				break;
-			case MEM_CLOCK_1333MHz:
-				/* TODO: DDR3 write DQ-DQS */
-				s->rt_dqs[ch][lane].tap = 7;
 				s->rt_dqs[ch][lane].pi = 0;
-				break;
-			default: /* not supported */
-				break;
+			} else { /* DDR3 */
+				/* TODO: DDR3 write DQ-DQS */
+				s->rt_dqs[ch][lane].tap = 6;
+				s->rt_dqs[ch][lane].pi = 2;
 			}
+			break;
+		case MEM_CLOCK_1066MHz:
+			/* TODO: DDR3 write DQ-DQS */
+			s->rt_dqs[ch][lane].tap = 5;
+			s->rt_dqs[ch][lane].pi = 2;
+			break;
+		case MEM_CLOCK_1333MHz:
+			/* TODO: DDR3 write DQ-DQS */
+			s->rt_dqs[ch][lane].tap = 7;
+			s->rt_dqs[ch][lane].pi = 0;
+			break;
+		default: /* not supported */
+			break;
 		}
 	}
 }
@@ -863,7 +860,7 @@
 	int ch, lane, rank;
 
 	FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
-		for (lane = 0; lane < 8; lane++) {
+		FOR_EACH_BYTELANE(lane) {
 			FOR_EACH_RANK_IN_CHANNEL(rank) {
 				rt_set_dqs(ch, lane, rank,
 					&s->rt_dqs[ch][lane]);
@@ -1140,7 +1137,7 @@
 		reg32 |= s->rcven_t[channel].min_common_coarse << 16;
 		MCHBAR32(0x400 * channel + 0x248) = reg32;
 
-		for (lane = 0; lane < 8; lane++) {
+	        FOR_EACH_BYTELANE(lane) {
 			medium |= s->rcven_t[channel].medium[lane]
 				<< (lane * 2);
 			coarse_offset |=
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c
index f386b6b..9a39b28 100644
--- a/src/northbridge/intel/x4x/raminit_tables.c
+++ b/src/northbridge/intel/x4x/raminit_tables.c
@@ -29,7 +29,7 @@
 	{4,  1, 0, 0, 0, 0}, /* ctrl3 */
 };
 
-const struct dll_setting default_ddr2_667_dqs[8] = {
+const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES] = {
 	{1,  5, 1, 1, 1, 0},
 	{1,  6, 1, 1, 1, 0},
 	{2,  0, 1, 1, 1, 0},
@@ -40,7 +40,7 @@
 	{14, 0, 1, 0, 0, 0},
 };
 
-const struct dll_setting default_ddr2_667_dq[8] = {
+const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES] = {
 	{9,  0, 0, 0, 1, 0},
 	{9,  1, 0, 0, 1, 0},
 	{9,  2, 0, 0, 1, 0},
@@ -62,7 +62,7 @@
 	{0,  5, 1, 1, 0, 0},
 };
 
-const struct dll_setting default_ddr2_800_dqs[8] = {
+const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES] = {
 	{2,  5, 1, 1, 1, 0},
 	{2,  6, 1, 1, 1, 0},
 	{3,  0, 1, 1, 1, 0},
@@ -73,7 +73,7 @@
 	{0,  3, 1, 1, 1, 0},
 };
 
-const struct dll_setting default_ddr2_800_dq[8] = {
+const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES] = {
 	{9,  3, 0, 0, 1, 0},
 	{9,  4, 0, 0, 1, 0},
 	{9,  5, 0, 0, 1, 0},
@@ -104,7 +104,7 @@
 		{3, 6, 0, 0, 0, 0}, }
 };
 
-const struct dll_setting default_ddr3_800_dqs[2][8] = {
+const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES] = {
 	{ /* 1N */
 		{12, 0, 1, 0, 0, 0},
 		{1, 1, 1, 1, 1, 0},
@@ -125,7 +125,7 @@
 		{0, 3, 1, 1, 1, 0}, }
 };
 
-const struct dll_setting default_ddr3_800_dq[2][8] = {
+const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES] = {
 	{ /* 1N */
 		{4, 1, 0, 0, 1, 0},
 		{6, 4, 0, 0, 1, 0},
@@ -165,7 +165,7 @@
 		{2, 2, 1, 1, 0, 0}, }
 };
 
-const struct dll_setting default_ddr3_1067_dqs[2][8] = {
+const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES] = {
 	{ /* 1N */
 		{2, 5, 1, 1, 1, 0},
 		{5, 1, 0, 0, 1, 0},
@@ -187,7 +187,7 @@
 	}
 };
 
-const struct dll_setting default_ddr3_1067_dq[2][8] = {
+const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES] = {
 	{ /* 1N */
 		{6, 5, 0, 0, 1, 0},
 		{9, 3, 1, 0, 1, 0},
@@ -228,7 +228,7 @@
 		{4, 5, 0, 0, 0, 0}, }
 };
 
-const struct dll_setting default_ddr3_1333_dqs[2][8] = {
+const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES] = {
 	{ /* 1N */
 		{2, 4, 1, 1, 1, 0},
 		{5, 1, 0, 0, 1, 0},
@@ -249,7 +249,7 @@
 		{9, 6, 0, 0, 1, 0}, }
 };
 
-const struct dll_setting default_ddr3_1333_dq[2][8] = {
+const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES] = {
 	{ /* 1N */
 		{6, 5, 0, 0, 1, 0},
 		{9, 3, 1, 0, 1, 0},
diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c
index ca66f29..e9a99fb 100644
--- a/src/northbridge/intel/x4x/rcven.c
+++ b/src/northbridge/intel/x4x/rcven.c
@@ -313,7 +313,7 @@
 	 * unitialised.
 	 */
 	u32 addr = 0;
-	struct rec_timing timing[8];
+	struct rec_timing timing[TOTAL_BYTELANES];
 	u8 mincoarse;
 
 	MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc;
@@ -329,7 +329,7 @@
 			addr = test_address(channel, rank);
 			break;
 		}
-		for (lane = 0; lane < 8; lane++) {
+		FOR_EACH_BYTELANE(lane) {
 			printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n",
 				channel, lane, addr);
 			timing[lane].coarse = (s->selected_timings.CAS + 1);
@@ -365,7 +365,7 @@
 		s->rcven_t[channel].min_common_coarse = mincoarse;
 		printk(BIOS_DEBUG, "Receive enable, final timings:\n");
 		/* Normalise coarse */
-		for (lane = 0; lane < 8; lane++) {
+		FOR_EACH_BYTELANE(lane) {
 			if (timing[lane].coarse == 0)
 				reg8 = 0;
 			else
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index 3d2fdae..e63a055 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -161,6 +161,7 @@
 
 #define TOTAL_CHANNELS 2
 #define TOTAL_DIMMS 4
+#define TOTAL_BYTELANES 8
 #define DIMMS_PER_CHANNEL (TOTAL_DIMMS / TOTAL_CHANNELS)
 #define RAW_CARD_UNPOPULATED 0xff
 #define RAW_CARD_POPULATED 0
@@ -215,6 +216,10 @@
 	FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r)
 #define FOR_EACH_POPULATED_RANK(dimms, ch, r) \
 	FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r)
+#define FOR_EACH_BYTELANE(l) \
+	for (l = 0; l < TOTAL_BYTELANES; l++)
+#define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \
+	FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l)
 
 #define DDR3_MAX_CAS 18
 
@@ -308,10 +313,10 @@
 
 struct rcven_timings {
 	u8 min_common_coarse;
-	u8 coarse_offset[8];
-	u8 medium[8];
-	u8 tap[8];
-	u8 pi[8];
+	u8 coarse_offset[TOTAL_BYTELANES];
+	u8 medium[TOTAL_BYTELANES];
+	u8 tap[TOTAL_BYTELANES];
+	u8 pi[TOTAL_BYTELANES];
 };
 
 /* The setup is up to two DIMMs per channel */
@@ -331,9 +336,9 @@
 	 * The rt_dqs delay register for rank 0 seems to be used
 	 * for all other ranks on the channel, so only save that
 	 */
-	struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][8];
-	struct dll_setting dqs_settings[TOTAL_CHANNELS][8];
-	struct dll_setting dq_settings[TOTAL_CHANNELS][8];
+	struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][TOTAL_BYTELANES];
+	struct dll_setting dqs_settings[TOTAL_CHANNELS][TOTAL_BYTELANES];
+	struct dll_setting dq_settings[TOTAL_CHANNELS][TOTAL_BYTELANES];
 };
 #define BOOT_PATH_NORMAL	0
 #define BOOT_PATH_WARM_RESET	1
@@ -367,16 +372,16 @@
 extern const struct dll_setting default_ddr3_800_ctrl[2][7];
 extern const struct dll_setting default_ddr3_1067_ctrl[2][7];
 extern const struct dll_setting default_ddr3_1333_ctrl[2][7];
-extern const struct dll_setting default_ddr2_667_dqs[8];
-extern const struct dll_setting default_ddr2_800_dqs[8];
-extern const struct dll_setting default_ddr3_800_dqs[2][8];
-extern const struct dll_setting default_ddr3_1067_dqs[2][8];
-extern const struct dll_setting default_ddr3_1333_dqs[2][8];
-extern const struct dll_setting default_ddr2_667_dq[8];
-extern const struct dll_setting default_ddr2_800_dq[8];
-extern const struct dll_setting default_ddr3_800_dq[2][8];
-extern const struct dll_setting default_ddr3_1067_dq[2][8];
-extern const struct dll_setting default_ddr3_1333_dq[2][8];
+extern const struct dll_setting default_ddr2_667_dqs[TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr2_800_dqs[TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr3_800_dqs[2][TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr3_1067_dqs[2][TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr3_1333_dqs[2][TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr2_667_dq[TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr2_800_dq[TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr3_800_dq[2][TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr3_1067_dq[2][TOTAL_BYTELANES];
+extern const struct dll_setting default_ddr3_1333_dq[2][TOTAL_BYTELANES];
 
 struct acpi_rsdp;
 #ifndef __SIMPLE_DEVICE__