Use common GCD function
Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78799
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c
index e3a5111..8726ac0 100644
--- a/src/drivers/analogix/anx7625/anx7625.c
+++ b/src/drivers/analogix/anx7625/anx7625.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
+#include <commonlib/bsd/gcd.h>
#include <delay.h>
#include <device/i2c_simple.h>
#include <edid.h>
@@ -152,30 +153,14 @@
return 0;
}
-static unsigned long gcd(unsigned long a, unsigned long b)
-{
- if (a == 0)
- return b;
-
- while (b != 0) {
- if (a > b)
- a = a - b;
- else
- b = b - a;
- }
-
- return a;
-}
-
/* Reduce fraction a/b */
-static void anx7625_reduction_of_a_fraction(unsigned long *_a,
- unsigned long *_b)
+static void anx7625_reduction_of_a_fraction(u32 *_a, u32 *_b)
{
- unsigned long gcd_num;
- unsigned long a = *_a, b = *_b, old_a, old_b;
+ u32 gcd_num;
+ u32 a = *_a, b = *_b, old_a, old_b;
u32 denom = 1;
- gcd_num = gcd(a, b);
+ gcd_num = gcd32(a, b);
a /= gcd_num;
b /= gcd_num;
@@ -198,9 +183,7 @@
*_b = b;
}
-static int anx7625_calculate_m_n(u32 pixelclock,
- unsigned long *m, unsigned long *n,
- uint8_t *pd)
+static int anx7625_calculate_m_n(u32 pixelclock, u32 *m, u32 *n, uint8_t *pd)
{
uint8_t post_divider = *pd;
if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
@@ -300,7 +283,7 @@
static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
{
- unsigned long m, n;
+ u32 m, n;
u16 htotal;
int ret;
uint8_t post_divider = 0;
@@ -311,7 +294,7 @@
return -1;
}
- ANXINFO("compute M(%lu), N(%lu), divider(%d).\n", m, n, post_divider);
+ ANXINFO("compute M(%u), N(%u), divider(%d).\n", m, n, post_divider);
/* configure pixel clock */
ret = anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_L,
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c
index 8a0e01c..eb79347 100644
--- a/src/northbridge/intel/ironlake/quickpath.c
+++ b/src/northbridge/intel/ironlake/quickpath.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <commonlib/bsd/gcd.h>
#include <console/console.h>
#include <cpu/intel/model_2065x/model_2065x.h>
#include <cpu/x86/msr.h>
@@ -11,31 +12,14 @@
#define NORTHBRIDGE PCI_DEV(0, 0, 0)
-static unsigned int gcd(unsigned int a, unsigned int b)
-{
- unsigned int t;
- if (a > b) {
- t = a;
- a = b;
- b = t;
- }
- /* invariant a < b. */
- while (a) {
- t = b % a;
- b = a;
- a = t;
- }
- return b;
-}
-
static inline int div_roundup(int a, int b)
{
return DIV_ROUND_UP(a, b);
}
-static unsigned int lcm(unsigned int a, unsigned int b)
+static u32 lcm(u32 a, u32 b)
{
- return (a * b) / gcd(a, b);
+ return (a * b) / gcd32(a, b);
}
struct stru1 {
@@ -65,7 +49,7 @@
int freq_max_reduced;
int freq3, freq4;
- g = gcd(freq1, freq2);
+ g = gcd32(freq1, freq2);
freq1_reduced = freq1 / g;
freq2_reduced = freq2 / g;
freq_min_reduced = MIN(freq1_reduced, freq2_reduced);
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index c2f93f5..d52fa2a 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <device/mmio.h>
#include <assert.h>
+#include <commonlib/bsd/gcd.h>
#include <console/console.h>
#include <delay.h>
+#include <device/mmio.h>
#include <lib.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
@@ -438,16 +439,6 @@
}
}
-static u32 clk_gcd(u32 a, u32 b)
-{
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
- return a;
-}
-
void rkclk_configure_i2s(unsigned int hz)
{
int n, d;
@@ -462,7 +453,7 @@
1 << 15 | 0 << 12 | 1 << 8 | 0 << 0));
/* set frac divider */
- v = clk_gcd(GPLL_HZ, hz);
+ v = gcd32(GPLL_HZ, hz);
n = (GPLL_HZ / v) & (0xffff);
d = (hz / v) & (0xffff);
assert(hz == GPLL_HZ / n * d);
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 75af695b..fbff5a7 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
+#include <commonlib/bsd/gcd.h>
#include <console/console.h>
-#include <device/mmio.h>
#include <delay.h>
+#include <device/mmio.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/grf.h>
@@ -776,16 +777,6 @@
return freq;
}
-static u32 clk_gcd(u32 a, u32 b)
-{
- while (b != 0) {
- int r = b;
- b = a % b;
- a = r;
- }
- return a;
-}
-
void rkclk_configure_i2s(unsigned int hz)
{
int n, d;
@@ -805,7 +796,7 @@
RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3));
/* set frac divider */
- v = clk_gcd(CPLL_HZ, hz);
+ v = gcd32(CPLL_HZ, hz);
n = (CPLL_HZ / v) & (0xffff);
d = (hz / v) & (0xffff);
assert(hz == (u64)CPLL_HZ * d / n);