src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 88cf47f..9a2c744 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -50,7 +50,7 @@
* The Secondary bus range for PCI0 lets the system
* know what bus values are allowed on the downstream
* side of this PCI bus if there is a PCI-PCI bridge.
- * PCI busses can have 256 secondary busses which
+ * PCI buses can have 256 secondary buses which
* range from [0-0xFF] but they do not need to be
* sequential.
*/